Vector 4 - Page 30

VECTOR 4
TECHNICAL INFORMATION
SECTION I - OVERVIEW OF CPU SYSTEM
Summary: The CPU System includes several different types of
circuitry. This ecircuitry supports the microprocessors and allows them
to interface with several major subsystems.
The CPU System can be described by reférencing the following blocks (subsystems)
from the SBC Block Diagram and Schematic: *
Block Schematic Subsystem
Diagram Notation Description
Number(s)
1 Al Clock: Generates different frequencies of clocking pulses
for SBC Subsystems.
1, 2 A2 WAIT State Decoder: Generates WAIT States so the
processor is synchronized with the VIDEO and CPU
Cyecles. |
3 A3 RESET: Represents System RESET function.
4 Ad Microprocessor Switehing Control: Switches operation
between microprocessors.
7, 8 |
22 A5 Microprocessors; CPUs of Vector 4. This subsystem also
handles various decoding functions.
20 A7 Data Bus Transceiver; This subsystem represents a single
chip which serves as a bi-directional driver for the Data
Bus.
26 Ab Microprocessor MUX: Multiplexes microprocessor address
lines.
The CPU portion of the SBC Block Diagram and Schematic is shown on the next
two pages.
* The blocks from the block diagram were designed to include a logical group of
SBC circuitry. Hence there is not necessarily a direct one to one relationship
between the block diagram number and the SBC Schematic letter/number. i.e. One
logical block may encompass several SBC subsystems. For these reasons the CPU,
RAM/PROM Memory, I/O and Video sections will describe the theory of operation by
primarily using the SBC Schematic notation.
09-01-82 7200-0001 II1-1