Vector 4 - Page 31

CPU portion of SBC Block Diagram (Exhibit VI-1)
ARTERLEAVE
CORTIOL
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vl
DISK
CONSROLLER
£ATEMmAL WONLTOR
COwmECTOn
o
s
i
vyra
e
CEnY PR
COommECTOR
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> |DATA BUS
CPU/VID
CONTROL AL1-AL7
INTERLEAVE
CONTROL
ROW/CCLUMN
CONTROL
CPU SELECT
INTERRUPT
CONTROL
CONTROL
D0-27
I 1-2