Vector 4 - Page 32

CPU portion of SBC Schematie (Exhibit VI-2 (B))
Schematic Schematic Schematic Block
Notation Subsystem Page Diagram
Title Number Number(s)
Al Clock Page 1 1
| A2 WAIT State Decoder Page 1 2
CPU System Al Microprocessor Switching
Control Page 1 4
A4 RESET Page 1 3
A5 Microprocessors Page 1 7, 8, 22
)
745113
741502
88 ENEL
(1) MREO
POFF
I
+ 5V
741514
U108
741502
use2
ug7
ue7
U10%
741574
74L.50C
{3) POCD
1) ICRD 741 SO0
&3
{1) BUSAK
{1 JOWR
e
———
+2 '3
2. RESISTOR VALUES ARE iN OMMS 1/a W, 57,
1. CAPACITOR VALUES ARE IN MICROFARACS .,
NCTES,UNLESS OTHERWISE SPECIFIED:
L
MHIGH (1)
69
80 ENBL (Y
88 ENAL (1)
+5v
M
ATCH
SET (3)
{3)
U101
+5
741502
74LS574
)
88 ENBL
CPU/VID (1,2)
74L.500
2N3906
U130 RS2 56
(2)
/VID (1, 2)
(3
(3) PROY
(3) TROY
74LS04
74LS 20
(1) BUSRO
(1) BUSAK
Q1
(1) 88 ENBL
ues
745367
2NQ06
U130 R’53,00
U8
1ORQ
741502 (2)
74L S04
MEMWR (2)
+ 5V
TORO (3!
S10
IOWR(3)
JOWR
{1)
Il 1-3