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LATCH]|

LATCHO|

LATCH1|

CPU/VID|

CPU|/VID

MHIGH]|

MHIGH

RAS]|

CAS

09-01-82

VECTOR

4

TECHNICAL

INFORMATION

This

signal

is

used

by

the

Video

System.

It

provides

the

signal

which

clocks

the

Reverse

Video

indicator

(U71).

Since

the

period

of

LATCH]

is

1

us,

each

scan

line

(for

one

character

cell)

can

be

evaluated

to

be

white

on

a

black

background

or

vice

versa.

The

LATCHO|

signal

is

used

by

the

Alpha/Graphic

MUX

(<C10>)

and

the

Graphic

Mode

Shift

Registers

(<C12>).

When

LATCHO|

is

LOW

the

Graphic

Mode

Shift

Registers

are

put

in

the

load

mode

and

16

bits

of

data

(2

byte

boundaries)

are

simultaneously

latched

into

the

registers.

The

"1B"

input

pin

of

the

Alpha/Graphic

MUX

is

also

activated

(dropping

LOW)

allowing

the

output

of

the

Graphic

Mode

Shift

Registers

(High

Resolution

Mode)

to

be

sent

through

pin

"2B".

This

signal

is

also

used

by

the

Alpha/Graphic

MUX.

In

this

case

when

the

signal

is

LOW

the

multiplexer

enables

the

"2A"

input

pin

causing

the

character

generator

information

to

be

transmitted

out

the

"2Y"

pin

(the

ALPH|/GRAPH

must

also

be

LOW).

This

signal

is

used

within

the

CPU/VID

MUX

Control

(<B2>),

the

Video

MUX

Lateh

(<C3>)

and

the

Dynamiec

RAM

Decoder

(<B5>)

Subsystems.

An

exact

description

the

function

of

this

signal

will

be

-

given

within

Section

2,1-B.

The

CPUI/VID

signal

is

used

within

the

CPU/VID

MUX

Control

(<B2>),

the

Video

MUX

Latch

(<C3>),

the

Dynamic

RAM

Decoder

(<{B5>)

and

the

Video

Controller

(<C1>)

Subsystems.

An

exact

description

the

function

of

this

signal

will

be

given

within

Section

2.1-B.

This

signal

is

used

within

the

CPU/VID

MUX

Control

(<B2>)

Subsystem.

Its

funetion

(along

with

CPU/VID

signals)

is

to

select

the

low

order

CPU

address

or

the

LOW

order

VIDEO

address.

This

is

accomplished

by

sending

out

an

enabling

signal

to

the

CPU/VIDEO

Address

MUX

(<B3>).

This

signal

performs

the

inverse

function

of

the

MHIGH]|

signal.

i.e.

Selects

the

high

order

CPU

address

with

the

high

order

VIDEO

address.

This

signal

is

a

2

MHz

signal

whieh

is

used

within

the

Dynamic

RAM

Subsystem

(<B4>).

It

provides

the

RAS

signal

for

the

RAM

so

that

the

memory

addresses

can

be

properly

multiplexed.

This

signal

is

used

within

the

Dynamic

RAM

and

Dynamic

RAM

Decoder

Subsystems.

CAS,

in

conjunction

with

other

control

signals,

produce

column

addresses

for

memory

locations.

7200-0001

II1-7