Vector 4 - Page 37

VECTOR GRAPHIC, INC.
B. WAIT State Decoder
*
In order to understand how the microprocessor and the other CPU Subsystems
function it is necessary to discuss the overall timing framework of the Single
Board Computer. Refer to Exhibit VI-1 and the Timing Diagram in Exhibit VI-3
while reading the rest of this section.
The microprocessors must have their T States spaced so that the
microprocessors use the data and address bus only during specified time slots.
This is necessary because the Video and CPU Systems use the same memory
module (128 K or 256 K Dynamic RAM).
The time slots are implemented by inserting WAIT States into the
microprocessors cycle when it is necessary to align the CPU and VIDEO
CYCLES. This is accomplished by selectively toggling the WAIT (Z80B) or
READY (8088-2) lines.
The WAIT line * is controlled by two S-100 lines (XRDY, PRDY), the Tone
Generator ready line (TRDY) and the output of the WAIT State Decoder
Subsystem (<A2>)., When any one of these lines go LOW the CPU is put in a
WAIT state.
The V-100 lines (modified S-100 lines) are utilized by the Disk Controller and
any other board located in the expansion slots. These bus lines are generally
tied HIGH.
The TRDY line goes LOW when the Tone Generator is enabled and is receiving
data. The Tone Generator stays in this state for 32 clock cyecles. Since it is
being elocked at 2 MHz (pin 14) this means the TRDY will be LOW for 16
microseconds during a typical Write operation.
The WAIT State Decoder Subsystem has several inputs. These input signals are
described below:
MREQ The inverse of the memory request signal generated by the CPU.
Also generated during Z80s Refresh cyele.
POEF| A Port Q signal used to chip select the video controller.
IORQ The inverse of the I/O request signal generated by the CPU.
88ENBL Generated by the Microprocessor Switching Control Subsystem
(<A3>). When this signal is HIGH the 8088-2 is in a HOLD State.
This discussion also applies to the 8088-2s READY line.
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