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VECTOR

4

TECHNICAL

INFORMATION

RFSH|

Generated

by

the

CPU

during

the

last

two

T

states

of

the

fetch

cycle,

The

SBC

does

not

use

this

signal

to

refresh

the

Dynamic

RAM.

Memory

refresh

is

handled

by

the

Video

Controller.

CPU/VID

(Via

internal

clock

circuit.)

This

signal

clocks

a

segment

of

the

WAIT

State

Decoder

Subsystem

Thes

so

that

the

WAIT

States

are

synchronized

with

the

CPU

and

VIDEO

Cyecles.

e

signals

are

interleaved

so

that

the

WAIT

State

Decoder

Subsystem

generates

the

following

controls:

*

-

The

Video

and

CPU

cycles

use

a

combined

total

of

5

T

States.

The

center

T

State

(on

boundary

of

Video

and

CPU

Cyecles)

is

necessarily

longer

than

the

others

(See

Exhibit

VI-5).

-

The

rising

edge

of

T3

occurs

at

the

beginning

of

the

VIDEO

Cyele.

-

The

CAS

signal

is

generated

so

that

it

is

HIGH

(active)

during

the

CPU

Cycle

and

LOW

durmg

the

VIDEO

Cyecle.

It

is

not

generated

during

the

CPU

cycle

if

the

microprocessor

is

not

accessing

memory

(no

MREQ]).

-

During

the

Z80B

Refresh

cycle

the

Z80B

internally

causes

RFSH|

and

MREQ|

to

go

LOW.

However,

because

of

the

nature

of

the

WAIT

State

Decoder

this

change

does

not

cause

the

generation

of

a

WAIT

State.

-

During

Ti

the

WAIT

line

is

pulled

LOW.*

The

WAIT

State

Decoder

Subsystem

does

not

generate

a

WAIT

State

if

one

of

following

circumstances

occurs:

1.

The

CPU

does

not

generate

a

MREQ|

during

T3.

This

occurs

when

the

microprocessor

is

doing

internal

operations.

2.

The

input

signal

CPU/VID

(via

the

clock

circuitry)

indicates

there

is

no

need

for

a

WAIT

State.

This

occurs

if

T;

falls

within

the

first

part

of

the

CPU

Cyecle

thus

resulting

in

T3

naturally

falling

at

the

beginning

of

the

VIDEO

Cyele.

This

T;

State

refers

to

the

first

cloeck

eycle

of

a

Z80B

Fetch,

Memory

Read

or

Memory

Write

instruction.

09-01-82

7200-0001

II1-9