Vector 4 - Page 41

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VECTOR

GRAPHIC

INC.

™

B.

Micerop

ors,

Microprocessor

MUX

and

Data

Bus

Transceive

The

Z80B

and

the

8088-2

have

many

of

its

primary

control

lines

gated

together

so

that

one

overall

group

of

control

signals

can

be

used

by

the

Serial/Parallel

Interfaces

and

other

subsystems.

Signal

MEMRD

MEMWR

IORQ

IOWR

IORD

MREQ

WR]

WR

RD|

RD

These

signals

are

listed

below:

Subsystem(s)

used

in

PROM

Decoder

Dynamic

RAM

Decoder

Microprocessor

Switching

Control

Keyboard

Interface,

Serial

Printer

Interface,

Modem

Interface,

Tone

Generator

Interface,

Parallel

Interface,

Expansion

Slot

Buffers,

Subsystem

Port

Register,

320

Mode

Decoder.

Keyboard

Interface,

Serial

Printer

Interface,

Modem

Interface,

Tone

Generator

Interface,

Parallel

Interface,

Expansion

Slot

Buffers.

WAIT

State

Decoder

Expansion

Slot

Buffers

Not

Used

Data

Bus

Transceiver

Expansion

Slot

Buffers

Address

lines

coming

from

the

microprocessors

are

multiplexed

so

that

there

is

no

address

line

contention.

This

is

accomplished

by

use

of

the

80ENABL|

and

88ENABL]|

signals

which

were

generated

by

RESET

Subsystem.

These

two

signals

are

used

as

enabling

signals

for

the

74LS244

buffers

and

74LS375

buffer/latches.

~

Both

microprocessors

data

lines

are

connected

to

the

Data

Bus

Transceiver.

This

chip

sends

or

receives

data

to

the

CPU

Data

Bus

(See

Exhibit

[I-3

for

a

description

of

the

Vector

4

bus

structure).

It

ecan

also

route

data

to

the

Address

Mapping

RAM

(<B1>).

o

1-12

7200-0001

09-01-82