Vector 4 - Page 42

EXHIBIT II-3 SBC BUS STRUCTURE
Numerous "Buses" are used on the Single Board Computer. The following chart describes the
four primary buses.
SCHEMATIC MANUAL
DESIGNATION DESIGNATION DESCRIPTION
DBY-DB? CPU Data Bus This is a data bus which receives or transmits data
to the Dynamic RAM and "non I/O devices". The
I/0 Data Bus intersects this bus through the I/O
Data Bus Transceiver.
10D¢-10D7 /O Data Bus This data bus connects several I/0 Devices (chips) to
the I/O Data Bus Transceiver. From this juncture
data bus information is sent to/from the CPU Data
Bus.
ZA(§-ZA15 CPU Address Bus These address lines go to the Expansion Slots, PROM
and various Port Registers. They are not
multiplexed with addresses used by the Video System.
MAQ-MAT Multiplexed Address Bus | This bus carries the multiplexed address lines from
the CPU/VIDEO Address MUX (<B3>) to the Dynamic
RAM. These lines are used exclusively for memory
(RAM) management.
Microprocessors
]
Data Bus
Transceiver
I
DB¢-DB7
]
I/0
Data Bus
Transceiver
ZA(-ZA15
MA17
MUX
[
10D
¢-
o IOD7
MA(J-MAT * |
Decoder Dynamic RAM
£
%
xex
%
e
=%
Expansion Port Parallel Video
PROM
Slots
Decoders
USARTS
Ports
Controller
* These lines are multiplexed into an actual MA-MA15 address range.
** These I/O Devices use some of the address lines from the CPU Address Bus. For instance
the Expansion slots use ZA9-ZA7 and the Video Controller uses only ZA{.
***
This
block
refers
to
two
subsystems
which
decode
address
lines
into
actual
port
select
signals (See Section 5.1).
I1 1-13