Vector 4 - Page 48

RAM/PROM and Video portions of SBC Schematic (Exhibit VI-2 (C))
R
Schematic Schematic Schematic Block
Notation Subsystem Page Diegram
Title Number Number(s)
B6 PROM Subsystem Page 2 31, 39
RAM/PROM System| B7 CPU RAM Buffers Page 2 41
B8 CPU MUX Latch Page 2 41
C3 Video MUX Latch Page 2 42
C4 Character Generators Page 2 43
Cs Alpha Mode Shift Registers Page 2 44
Cé6 320 Mapping RAM Page 2 35
) C7 Gray/Color Decoder Page 2 28
Video
System
C8
Video
Bit
MUX
Page
2
38
C9 Video Bit Latch Page 2 40
C10 Alpha/Graphic MUX Pege 2 46
C11 4-Bit D/A - Page 2 45
C12 Graphic Mode Shift
Registers Page 2 33
C13 Video Combiner Pege 2 46, 47, 48
+5v CHRE/CHR1(3)
(1) Lg-L3
74LS30
ve
74{5374
uss
CS
U
2732 HSYNC sl sTNG
or
SR
g
(2764) (1) {1) VSYNC 41jvSYNC
Q ALPHAGRAPH +
uot
CATCH @
13 R38
1%0
DIGIGRY
B7 (W LATCH 88
U7 313
ALPH/GRAPH
+
_4>_ us1 (3
7451%7
13
U129
tM 3046
uzs
7415193
ACTIVE NIGH
8
<5 AL o)
u32 u1s u16 741508
74159% 741595 741595
VSYNC L1
MSYNC L
T urn1o
7405175 INTENSITY
(2) vSYNC
t2) HMSYNC
112
(3) 1009 ~-1003
(1 2A8
03
Gw
y
7415158
aC/BC 12)
u73
74
74 LS00 LS670
II 2-5