Vector 4 - Page 47

RAM/PROM,
and
Video
portions
of
SBC
Schematic
(Exhibit
VI-2
(C))
Schematic Schematic Schematic Block
Notation Subsystem Page Diagram
Title Number Number(s)
B4 Dynamic RAM Page 2 32, 34, 36, 37
BS Dynamic RAM Decoder Page 2 29
RAM/PROM System | B6 PROM Subsystem Page 2 31, 39
B7 CPU RAM Buffers Page 2 41
B8 CPU MUX Latch Page 2 41
C3 Video MUX Latch Page 2 2
. C6 320 Mapping RAM Pauge 2 35
Video System C12 Graphic Mode Shift
Registers Page 2 33
oey-
)
{13 741504
2an-ZA1% us
1 . ROMENBL
{n
3
us
MEMORY EXPANSION BOARD m
a
o
~Z
Qg
®
@)
(2)
MAP — MAT
87 I LATC =
Uiz
22
27
18
PIN
DIiP
(2) WR?
{2) CAS
u78
U3 ule U1s
74LS0C4 74LS95 74L59% 74L 595
74LS00 74LS04 BS
)
(1) CPYVID - () CAS
741508 7aL 740500
74L508
2
{21
Ud
WRQ (2)
(21
2)
(3) 100@-127C23
{2)
{2) MA1
(2) 2
{2) maA1
8
— e (1) CPU/VID
(1) MA17 MATT (2)
(2)
= MA17 (2) 1)
(1) TOWR
‘3 PICD
(3) PTEF
(2 MA17
741510
II 2-4