Vector 4 - Page 56

VECTOR 4
TECHNICAL INFORMATION
2.2 HOW THE DYNAMIC RAM MEMORY IS
ORGANIZED
Summary: This section describes how the multiplexed CPU and VIDEO
addresses are used by the Dynamic RAM Subsystem.
The previous sections discussed how the two different memory users (CPU and
VIDEO) have their cycles interlaced so that there is no contention on the
Multiplexed Address Bus. It was shown that this is accomplished by the
implementation of two master time slots or cycles:
CPU
VIDEO
The nature of these time slots and how they are controlled was discussed in Section
L.l1. Once the time slots are established it was shown that it was necessary to
multiplex the address lines going to the Dynamic RAM. This multiplexing was
accomplished by the subsystems described in the previous section: CPU/VID MUX
Control and CPU/VIDEO Address MUX. , |
The address lines coming from this multiplexing are strobed into the exact memory
locations by signals generated by the Clock and Dynamic RAM Decoder Subsystems.
A..DynmmLRAM_llecmm
The Dynamic RAM decoder is responsible for generating a specific set of CAS
and WRITE signals. These signals are interlaced with the RAS| signal (from
Clock Subsystem) to provide strobes for the MAO-MAT lines.
This interleaving is described below for a Memory WRITE (CPU Cycle) and a
Memory Read (VIDEO Cyecle). A Memory READ (CPU Cyecle) is not described
but employs similar concepts.
NOTE: There is no Memory Write (VIDEO Cycle) since the Video System only
ngads_ RAM data. The MALT signal which is used by the Dynamic RAM Decoder
is a result of a special decoding procedure. See Section 2,1-B for a description
of the CPU/VIDEO Address MUX.
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