Vector 4 - Page 57

VECTOR GRAPHIC INC.
B.
Memory WRITE (CPU Cycle)
During a WRITE operation the MEMWR is HIGH along with the control
signal CPU/VID|. These signals are combined at a NAND gate (U87) with
the resultant signal inverted and sent to a group of NAND gates (74LS00).
At this juncture they provide the gating for the generation of WRO0|, WR1l|,
WR2| and WR3|. These signals provide a WRITE control for the
appropriate block of RAM memory.
The multiplexed lines MA17, MA17| (Through use of CPU/VID signals) and
the non-multiplexed lines ZA0, ZAO]| provide the other inputs that are
decoded to generate the WRITE control signal.
The memory blocks also require generation of a CAS and RAS signal. The
RAS signal is a constant clock pulse which is sent directly to all RAM
memory blocks (See Timing diagram in Part VI). Therefore there must be
four different CAS signals so that a specific memory block can be
addressed. This is accomplished by using the CAS signal generated by the
WAIT State Subsystem. This results in two control functions:
-Each memory block has a unique CAS signal.
-A memory block is only accessed when the CPU is in the proper time
slot.
.
Memory READ (VIDEO Cyecle)
As with a Memory WRITE (CPU Cyele) this function requires the
generation of a specific CAS and RAS signal. The RAS signal is used
exactly as it is used during a Memory WRITE (CPU Cyecle). However, the
generation of CAS requires additional ecircuitry. This is necessary because
one VIDEO address must generate two bytes of data (See Exhibit VI-5).
The circuitry shown on page 2, quadrant A-7 of the SBC schematic
acceomplishes -this task.
These gates require four input signalss CPU|/VID, MA17], 2M and MA17.
The combination of these signals result in the generation of two control
signals which are used to toggle a pair of CAS lines. Hence, when a
VIDEO Address is sent to the Dynamic RAM this circuitry accomplishes
two functions:
-Two memory blocks have a unique CAS signal.
-A pair of memory blocks is only accessed when the VIDEO is in the
proper time slot.
Dynam R A CPU RAM Buyffe 9 g P{] V _Latch
The Dynamic RAM is logically organized into 2 K blocks (see Exhibit II-4).
- These blocks are addressed through the use of the Address Mapping RAM and
II 2-14
Dynamic RAM Decoder Subsystems along with the RAS| control signal. This
process was described in the previous section.
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