Vector 4 - Page 58

VECTOR 4
TECHNICAL INFORMATION
The Dynamiec RAM is physically arranged in two rows of eight chips. The top
row responds to even addresses while the bottom row is accessed by odd
addresses. This arrangement is also used on the memory expansion board.
Exhibit II-7 shows how the location of individual 4164s relate to the memory
address structure.
During the CPU Cycle the Dynamic RAM sends out (for a Memory READ) 8-bits
-of data to one of the CPU RAM Buffers. This buffer is simultaneously enabled
resulting in the 8-bit block of data being routed to the CPU MUX Latch. The
Latch is clocked with the LATCH control signal so the data is received and
held until the microprocessor can read the lines. This occurs typically during
the VIDEO time slot (T State 3).
The Dynamic RAM is refreshed when all its row addresses (256 with a 128 K
system) are referenced within a 4 ms. period. This is accomplished by the
video circuitry which sequentially reads bytes from the RAM.
09-01-82 7200-0001 II 2-15