Vector 4 - Page 67

CPU, RAM/PROM and Yideo portions of SBC Schematic (Exhibit VI-2 (B))
Schematic Schematic Schematic Block
Notation Subsystem Page Diagram
Title Number Number(s)
Ab Microprocessor )
CPU
System
MUX
.
Page
1
26
®
A7 Data Bus Transcelver Page 1 20
Bl
Address Mapping RAM Page 1 21
B2 CPU/Video MUX
RAM/PROM System Control Page 1 29
B3
CPU/Video Address
MUX Page 1 29
. C1 Video Controller Page 1 27
Video System C2 Video MUX Page 1 30
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II 3-4