Vector 4 - Page 68

RAM/PROM and Yideo portions of SBC Schematic (Exhibit VI-2 (C))
Schematic Schematic Schematic Block
Notation Subsystem Page Diagram
Title Number Number(s)
B4 Dynamic RAM Page 2 32, 34, 36, 37
BS Dynamic RAM Decoder Page 2 29
RAM/PROM System | B6 PROM Subsystem Page 2 31, 39
B7 CPU RAM Buffers Page 2 41
B8 CPU MUX Latch Page 2 41
C3 Video MUX Latch Page 2 42
. C6 320 Mapping RAM Page 2 35
Video System C12 Graphic Mode Shift
Registers Page 2 33
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1)
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ZM‘-‘-ZM.‘.\
(")
MEMORY EXPANSION BOARD
16
PIN
DIP
(2)
MAD — MAT
22
27
18
PIN
DIP
M A
(2) WRO (2) WR?
(2) (2)CAS1
1M
74LS00 74LSO4 BS
1) MEMWR
1) CPYVD
ue?7
74L508 74LS00 74LS00
(2
(2)
(21_2A2
(2) MA17
U4
U4
(2}
{2) MA1
(2)
{(2) Ma17
ue7 -
— (1) TPU/VID
(1) MA17 ——fokiol -2l ed TRTT (2)
19 (2 FATY
= MA17 (2) 0,
{2y a7
74L 510
741508
Mm
74LS04
us
ROMENBL
)
.
—
u78
74LS04
us
74,830
ué
(VLATCH
u1s
74L 585
(3) IODO-10D1
(1Y 258
(1 2A
,AOWR
PICD
J PIEF
74 LS00
U34
745374
74L S€
I 3-5