Vector 4 - Page 70

3.1
A.
VECTOR 4
TECHNICAL INFORMATION
HOW THE VIDEO CONTROLLER AND
VIDEO MUX FUNCTION
Summary:
The
Video
Controller
provides
several
functions.
These
include
generating
the
video
addresses
which
are
then
multiplexed
through
the
Video
MUX
and
the
CPU/VIDEO
Address
MUX.
Yideo Controlier
The Video Controller is a 6545A-1 CRT Controller chip. It is used in the SBC
to provide the following functions.
1. Generate the addresses which are used by the various VIDEO modes:
Alpha, Gray Scale, High Resolution and Color modes.
2. Generate the Refresh addresses for the Dynamic RAM.
3. Generate the Vertical and Horizontal Syne signals.
The
data
pins
of
this
chip
are
connected
to
the
I/O
Data
Bus.
The
control
pins
of
the
6545A-1
are
attached
to
a
variety
of
51gnals
which
are
deseribed
below,
External {6545A-1 | Function
Signal Pin
ZAQ RS This pin is used to select internal registers. A HIGH on this pin allows the
contents of the Address Register to act as a poijpnter to the actual
Configuration Register. Since the ZAO0 signal is part of the Port Address
(POEF{) it can be used to toggle between Port 0EH and OFH. Section V
shows how this port decoding procedure is used to address the USARTS.
A LOW permits writing to the Address Register or a reading from the Status
Register,
IOWR R/w The Read/Write select pin. A LOW permits the microprocessor to write the
data to the 6545A-1.
2M 02 System clock.
CPU/VID|CCLCK | This signal establishes the time base for release of the video data addresses
from the address lines. For this reason it is connected to the CPU/VID line
which controls the interleaving of the CPU and VIDEO Cycles.
POEF CS The chip select pin which is controlled by the decoded port address (from the
| Port Decoder 0 Subsystem). This port address is further decoded by the ZAOD
signal (Used by the 6545A-1, RS pin).
+5
o
W
If active this pin would ¢lear all internal scan counter circuits.
09-01-82
-
7200-0001
|
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