Vector 4 - Page 98

VECTOR 4
TECHNICAL INFORMATION
°.1 HOW THE PORT CONTROL SIGNALS
ARE GENERATED
Summary: The SBC has several subsystems which generate signals that
are used as chip select and port select controls. This section
describes three SBC Subsystems which accomplish this task.
A. Subsystem Port Register
The Subsystem Port Register is a 7T4LS273 which is used to generate five
control signals. The function of these control signals is briefly given in the
following chart:
Signal r (0t
- ROMENBL)| Enables or disables PROM Memory (See Section 2.3).
ALPH|/GRAPH Selects Alpha or Graphic Video Mode (See Sections 3.1-C, 3.2,
3a3-=A).
320/160] ~ Selects 320 or 160 Graphic Video Mode (See Sections 3.3-A,
B.
DIG|/GRY Controls video blanking during ‘Alpha or Graphic Video Mode
(See Sections 3.2, 3.3-B).
This chip uses the I/O Data Bus as do all serial ports. The I/O Data Bus is
multiplexed with the CPU Data Bus through the use of the I/O Data Bus
Transceiver. See Exhibit [I-3 for a diagram of the SBC Bus system.
B. Port Decoders
There are two port decoders used on the SBC. These decoders generate the
enabling signals used to chip select a variety of ports. A list of the port
51gnals generated along with a brief description of the signal is given in Exhibit
09-01-82 7200-0001 II 5-7