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General| Category | I/O Systems |
|---|---|
| Manufacturer | Winbond |
| Model | W83627DHG |
| Type | Super I/O |
| Interface | LPC |
| GPIO | Yes |
| Temperature Sensor | Yes |
| Fan Control | Yes |
| Voltage Monitoring | Yes |
| Hardware Monitoring | Yes |
| Serial Ports | 2 |
| Parallel Port | Yes |
| Floppy Disk Controller | Yes |
| Keyboard Controller | Yes |
| Operating Voltage | 3.3V |
| Operating Temperature | 0°C to 70°C |
Lists general capabilities like LPC spec compliance, hardware monitor, ACPI support.
Details floppy disk controller capabilities like data rates and drive support.
Describes two high-speed serial ports with 16550 compatibility and FIFO.
Covers IBM parallel, PS/2, EPP, and ECP modes with current protection.
Details 8042-based controller, PS/2 mouse support, and Port 92 functions.
Explains Smart Fan control, temperature sensing, voltage monitoring, and I2C interface.
Supports up to 8MB SPI Flash Memory with clock up to 33 MHz.
Supports IrDA 1.0 SIR and SHARP ASK-IR protocols.
Describes 40 programmable GPIO ports with optional watchdog and LED functions.
Supports wake-up events from keyboard, mouse, and ACPI sleeping states.
Supports SST temperature and voltage sensing via a serial bus.
Supports Intel CPU PECI 1.0 specification for temperature sensing.
Mentions 128-pin QFP and Pb-free/RoHS compliance.
Provides detailed pin assignments for W83627DHG UBC and UBE/UBF versions.
Explains the function and type of each pin (e.g., AOUT, AIN, INcd, I/O8t).
Defines symbols, pins, I/O, and descriptions for LPC bus signals.
Details symbols, pins, I/O, and descriptions for Floppy Disk Controller interface.
Lists pin definitions for SPP, EPP, and ECP modes.
Describes pins for serial communication and infrared functions.
Details pins for Keyboard Controller interface.
Explains SPI interface signals (SI, SO, SCK) and operation.
Describes pins related to temperature, fan speed, and voltage monitoring.
Defines pins for Intel CPU PECI interface.
Defines pins for Simple Serial Transport interface.
Details ACPI power control pins like PSIN#, PSOUT#, SUSB#, PSON#.
Covers SMBus, GPIO power sources, and GPIO interfaces (2-6).
Lists power supply pins (3VSB, VBAT, 3VCC, AVCC, CPUD-(AGND), VSS, Vtt).
Lists twelve logical devices and their corresponding functions and I/O base addresses.
Details the steps to enter, configure, and exit Extended Function Mode.
Explains monitoring of voltages, fan speeds, temperatures, and case open detection.
Describes LPC and I2C interfaces for accessing hardware monitor registers.
Details voltage measurement inputs and external circuits for range extension.
Explains monitoring temperature from thermistors or thermal diodes in voltage/current mode.
Lists SST commands for voltage and temperature sensing.
Guides on enabling PECI functionalities and programming registers for temperature reading.
Details fan speed measurement calculation and fan speed control modes (PWM/DC).
Explains Thermal Cruise™, Fan Speed Cruise™, and SMART Fan™ III modes.
Describes SMI# and OVT# interrupt modes for voltage, fan count, and temperature events.
Explains the feature to detect if the computer case is opened.
Details the alarm output function for out-of-range monitored parameters.
Defines the address port for hardware monitor registers.
Defines the data port for reading/writing value RAM and registers.
Configures SYSFANOUT PWM output frequency using clock source and pre-scaler.
Selects the output value for SYSFANOUT, supporting PWM duty cycle or DC voltage.
Configures CPUFANOUT0 PWM output frequency using clock source and pre-scaler.
Selects the output value for CPUFANOUT0, supporting PWM duty cycle or DC voltage.
Controls mode and output type selection for SYSFANOUT and CPUFANOUT0.
Sets target temperature for SYSTIN or target speed for SYSFANIN.
Sets target temperature for CPUTIN or target speed for CPUFANIN0.
Defines tolerance for target temperature or target speed settings.
Sets the minimum fan output value for SYSFANOUT in Thermal Cruise mode.
Sets the minimum fan output value for CPUFANOUT0 in Thermal Cruise/SMART Fan III.
Sets the minimum fan output value to turn on the fan for SYSFANOUT.
Sets the minimum fan output value to turn on the fan for CPUFANOUT0.
Determines the time for SYSFANOUT value to fall from stop value to zero.
Determines time for CPUFANOUT0 value to fall from stop value to zero.
Determines time taken for FANOUT to decrease its value by one step.
Determines time taken for FANOUT to increase its value by one step.
Configures AUXFANOUT PWM output frequency using clock source and pre-scaler.
Selects output value for AUXFANOUT, supporting PWM duty cycle or DC voltage.
Configures output mode and minimum value settings for various fan outputs.
Sets target temperature for AUXTIN or target speed for AUXFANIN0.
Defines tolerance for AUXTIN target temperature or AUXFANIN0 target speed.
Sets the minimum fan output value for AUXFANOUT in Thermal Cruise mode.
Sets the minimum fan output value to turn on the fan for AUXFANOUT.
Determines time for AUXFANOUT value to fall from stop value to zero.
Configures OVT# interrupt modes and enables/disables temperature sensor outputs.
Registers reserved for future use.
Stores readings for CPUVCORE, VIN0-3, AVCC, 3VCC, SYSTIN, SYSFANIN, CPUFANIN0.
Controls system start, SMI# enable, interrupt clearing, and monitoring operations.
Indicates status of fan count limits and temperature thresholds for various sensors.
Reports CPUTIN, SYSTIN over-target temperature, AUXTIN limits, and case open status.
Disables corresponding interrupt status bits for SMI interrupt.
Disables corresponding interrupt status bits for SMI interrupt.
Contains CASEOPEN clear control and SMI# interrupt disable bits.
Configures fan divisors and input control for CPUFANIN1 and AUXFANIN1.
Sets the serial bus address for devices like SST and PECI.
Selects temperature source for CPUFANOUT0 and AUXFANOUT monitoring.
Selects temperature source for CPUFANOUT1 monitoring.
Configures divisor bits for AUXFANIN0 and selects ADC clock input.
Controls SMI# output type and enables/disables OVT# output for CPUTIN/AUXTIN.
Configures fan input control and output value settings for various fans.
Selects banks for registers 50h-5Fh and controls BEEP output.
Provides the Winbond Vendor ID.
Controls BEEP output for CPUFANIN0, SYSFANIN, CPUTIN, SYSTIN, 3VCC, and AVCC.
Controls BEEP output for VIN0, VIN1, VIN2, VIN3, AUXFANIN0, CASEOPEN, and VIN4.
Displays the Winbond Chip ID number.
Selects diode mode for temperature sensors (AUXTIN, CPUTIN, SYSTIN).
Controls VBAT monitoring and fan divisor settings.
Enables critical temperature protection and current mode for fans and sensors.
Configures CPUFANOUT1 PWM output frequency using clock source and pre-scaler.
Selects output value for CPUFANOUT1, supporting PWM duty cycle or DC voltage.
Configures CPUFANOUT1 output mode, mode control, and tolerance settings.
Sets target temperature for CPUFANIN1 or target speed for CPUFANIN1.
Sets the minimum fan output value for CPUFANOUT1 in Thermal Cruise/SMART Fan III.
Sets the minimum fan output value to turn on the fan for CPUFANOUT1.
Determines time for CPUFANOUT1 value to fall from stop value to zero.
Sets the maximum fan output value for CPUFANOUT0 in SMART Fan III mode.
Defines the step value for increasing/decreasing CPUFANOUT0 output.
Sets the maximum fan output value for CPUFANOUT1 in SMART Fan III mode.
Defines the step value for increasing/decreasing CPUFANOUT1 output.
Sets critical temperature for SYSFANOUT; fan works at full speed above threshold.
Sets critical temperature for CPUFANOUT0; fan works at full speed above threshold.
Sets critical temperature for AUXFANOUT; fan works at full speed above threshold.
Sets critical temperature for CPUFANOUT1; fan works at full speed above threshold.
Reads the high byte of CPUTIN temperature sensor data.
Reads the low byte of CPUTIN temperature sensor data.
Configures CPUTIN sensor operation, including OVT# mode and fault detection.
Sets the high byte of CPUTIN temperature hysteresis.
Sets the low byte of CPUTIN temperature hysteresis.
Sets the high byte of CPUTIN over-temperature threshold.
Sets the low byte of CPUTIN over-temperature threshold.
Reads the high byte of AUXTIN temperature sensor data.
Reads the low byte of AUXTIN temperature sensor data.
Configures AUXTIN sensor operation, including OVT# mode and fault detection.
Sets the high byte of AUXTIN temperature hysteresis.
Sets the low byte of AUXTIN temperature hysteresis.
Sets the high byte of AUXTIN over-temperature threshold.
Sets the low byte of AUXTIN over-temperature threshold.
Reports fan count limits and temperature status for various sensors.
Disables corresponding interrupt status bits for SMI interrupt.
Controls BEEP output for VBAT, 3VSB, and user-defined events.
Applies an offset to the SYSTIN temperature reading.
Applies an offset to the CPUTIN temperature reading.
Applies an offset to the AUXTIN temperature reading.
Indicates status of fan counts and CPUTIN/SYSTIN temperature sensor status.
Reports SYSTIN status, voltage statuses (3VCC, AVCC, VIN0), and case open status.
Reports AUXFANIN1 status, VIN2/VIN3 voltage statuses, and smart fan warning status.
Explains how to use SPI instructions via LPC I/O read/write commands.
Defines the SPI address map and the functions of each byte.
Provides examples for erasing, reading, and programming SPI flash devices.
Integrates logic for floppy disk control, FIFO, data separator, and precompensation.
Lists and describes FDC commands with their symbol descriptions.
Details status, data, and control registers for the FDC.
Controls asynchronous data communication parameters like data length, stop bit, parity.
Provides information on data transfer status like overrun error, parity error, and FIFO status.
Controls handshake pins and diagnostic mode for UART.
Reflects the current state of handshake peripheral input pins.
Controls FIFO functions including enable, reset, and interrupt levels.
Enables and disables controller interrupts separately.
Sets baud rate by dividing a base frequency with a programmable divisor.
A temporary register for user access and definition.
Supports SPP, BPP, EPP, and ECP modes for parallel port connection.
Details EPP registers, bit maps, and operational modes (Version 1.9 and 1.7).
Covers ECP modes (SPP, PS/2, FIFO, ECP, EPP, Test, Config) and register maps.
Explains RLE decompression and FIFO usage in ECP mode.
Details DMA transfers and programmed I/O operations for ECP/Parallel Port FIFOs.
Provides functions to interface CPU with keyboard/PS/2 mouse.
Describes the 8-bit read-only output buffer for scan codes and commands.
Describes the 8-bit write-only input buffer for data and command writes.
Holds information about keyboard controller and interface status.
Lists commands for reading/writing keyboard data and controlling its interface.
Details hardware control logic for GATEA20 and KBRESET signals.
Controls GATEA20 and KBRESET functions.
Explains PME# signal connection and lists supported wake-up events.
Describes ACPI function via power control pins like PSIN#, PSOUT#, SUSB#, PSON#.
Illustrates normal operation and ACPI state transitions related to PSON#.
Details system recovery to a pre-defined state after AC power failure.
Explains keyboard wake-up function and password setup for specific key combinations.
Describes mouse wake-up functions based on button clicks or movements.
Details RSMRST# signal behavior related to 3VSB power status.
Explains PWROK signal generation based on 3VCC voltage and delay parameters.
Illustrates the interrelation of power-related signals for UBE/UBF versions.
Describes Quiet and Continuous modes for SERIRQ start frame timing.
Details the structure of IRQ/Data frames and sampling periods.
Explains how the host controller terminates SERIRQ with a Stop frame.
Describes TTL, GTL, and AMD VRM input level settings.
Configures VID pins for output mode and sets data via data register.
Covers global control functions like software reset, logical device selection, and power down.
Details registers for Floppy Disk Controller (FDC) functionality.
Details registers for Parallel Port modes and IRQ/DRQ selection.
Details registers for UART A clock source and IRQ selection.
Details registers for UART B clock source and IRQ selection.
Details registers for KBC clock rate, Port 92, GATEA20, and KBRST control.
Details registers for SPI configuration, clock rate, and I/O base address.
Details registers for GPIO6 I/O, data, inversion, and event status.
Configures Watchdog Timer modes, count modes, and Power LED modes.
Details GPIO registers for I/O, data, inversion, and event status.
Details ACPI configuration bits for wake-up events and power control.
Configures hardware monitor base address and IRQ resource.
Configures PECI agent settings, TBase registers, and PECI warning flags.
Lists the extreme voltage, temperature, and operating conditions for the device.
Details DC electrical parameters like input/output voltages, currents, and leakage.
Provides timing diagrams and parameters for AC power failure resume and VSBGATE# signals.
Specifies timing parameters for clock inputs like cycle jitter and duty cycle.
Details timing parameters for PECI and SST interfaces.
Specifies timing parameters for SPI interface operations.
Details timing parameters for SMBus communication.
Provides timing parameters for FDC signals like DIR#, STEP#, INDEX#, RDATA#, WD#.
Details timing parameters for UART and Parallel Port operations.
Specifies timing parameters for Parallel Port FIFO operations.
Provides timing parameters for ECP Parallel Port forward direction.
Provides timing parameters for ECP Parallel Port reverse direction.
Details timing parameters for Keyboard Controller interface operations.
Specifies timing parameters for GPIO operations.
Details timing parameters for the LPC interface.
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