Acer G195W - Page 30

SPEC NO.
MT190AW02 V.Y
PAGE
12/23
c. Input signal timing
Support Input Timing Table
Item Description Min. Typ. Max. Unit
period 17.24 22.5 27 nS Clock
Dclk
frequency 37 44.4 58 MHz
T
V_TOTAL
V total line number 905 926 942 T
H_TOTAL
T
V_DATA
Data duration
－
900
－
T
H_TOTAL
T
VB
V-blank 5 26
－
T
H_TOTAL
Vertical
f
V
frequency 50 60 75 Hz
T
H_TOTAL
H total pixel number 752 800 968 DClk
T
H_DATA
Data duration
－
720
－
DClk
Horizontal
T
HB
H-blank 32 80
－
DClk
Note: Because this module is operated by DE only mode, Hsync and Vsync input signals should be set
to low Logic level or ground. Otherwise, this module would operate abnormally.
INPUT SIGNAL TIMING DIAGRAM
Tv
Tvd Tvb
Th
Tc
Thb Thd
DE
DCLK
DE
DATA