Aim-TTI CPX400D - Status Model Overview

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Bit 7 -
Not used.
Bit 6 - RQS/MSS. This bit, as defined by IEEE Std. 488.2, contains both the Requesting Service
message and the Master Status Summary message. RQS is returned in response to a
Serial Poll and MSS is returned in response to the *STB? command.
Bit 5 - ESB. The Event Status Bit. This bit is set if any bits set in the Standard Event Status
Register correspond to bits set in the Standard Event Status Enable Register.
Bit 4 - MAV. The Message Available Bit. This will be set when the instrument has a response
message formatted and ready to send to the controller. The bit will be cleared after the
Response Message Terminator has been sent.
Bit 3 -
Not used.
Bit 2 -
Not used.
Bit 1 - LIM2. This will be set if any bits in Limit Event Status Register 2 are set and
corresponding bits are set in Limit Event Status Enable Register 2.
Bit 0 - LIM1. This will be set if any bits in Limit Event Status Register 1 are set and
corresponding bits are set in Limit Event Status Enable Register 1.
Status Model