Aiwa CSD-ED88 - Page 26

IC, LC78622ED
Pin No.
Pin Name
I/O
Description
1
DEH
I
Defect detection signal (DEF) input terminal.
2
TAI I
A pull-down resistor is built in. (Connected to OV)
3
PDO
External VCO control phase comparator output.
4 VVSS
-
Connected to internal VCO of PEL. (Connected to OV)
5
ISET
I
PDO output current adjustment resistor connection.
6
VVDD
-
Voltage terminal for internal VCO of PEE.
7
FR
I
VCO frequency range adjustment.
8
vss
-
Digital system ground. (Connected to OV)
9
EFMO 0
EFM signal output pin.
10
EFMIN
I
EFM signal input pin.
11
T2
I
Test pin. (Connected to OV)
12
CLV+
0
Disc motor control output.
13
CLV-
14
V/P 0
Rough servo/phase control automatic switching monitor output.
Rough servo at "H". Phase control at "E".
15
HFL
I
Track detection signal input.
16
TES
I
Tracking error signal input.
17
TOFF
0
Tracking off output.
18
TGL 0
Tracking gain switching output.
19
JP+
0
Track jump output.
20
JP-
21
PCK
0
EFM data playback monitor. Outputs 4.3218MHz when the phase is locked. (Not used)
22
FSEQ
0
Synchronization signal detection output. Outputs a "H" level when the synchronization
signal detected from EFM signal and internally generated synchronization signal
range.(Not used)
23
VDD
-
Digital system power supply.
24
SL+
Serial data command sled signal output terminal from microprocessor.
25
SL-
26
NC
-
Not used.
27
PUIN
CD pickup inside limit switch. (Not used)
28
NC
-
Not used.
29
EMPH
o
De-emphasis monitor pin. A "H" level indicates playback of a de-emphasis disc.
(Not used)
30
C2F o
C2 flag output. (Not used)
31
DOUT 0
Digital output (EIAJ format). (Not used)
32
T3
I
Test input. (Connected to OV)
33
T4 I
Test input. (Connected to OV)
34
NC
-
Not used.
35
MUTEL
o
Eeft channel mute output. (Not used)
36
LVDD
-
Eeft channel power supply.
37
ECHO
o
Eeft channel output.
39