Akai MPC3000 - Page 53

РМ Мо.
1,15,25,30,31,44
60,61,71,81,90,91
36
РОНТ МАМЕ
САЗ-СА1 ||| Host CPU address bus.
100,111,120
2
6,16,27,35,45,54 | Vss
62,75,88, 106,110
7-14,17-24
26
28
29
32
33 IOWN
34
36
37 [Rout [9|
38 кост __|0|
WRAMWN
ROMWGN
TEST OUT
=
t
92-99,101-105 Wo-W15
112~114
107
108
109
115
116
118
119
FUNCTION
| | | Chip select input.
To be grounded.
Host CPU, DMA data bus.
| O | DMA request output (High active).
| | | ОМА acknowledge input (low active).
| | | To be used for function test.
| | | Host CPU, DMA read input (iow active).
EN Host CPU, DMA write input (low active).
NN System reset signal input (low active).
| о | Host CPU read/write ready output (low active)
Serial data output for D/A converter
Serial data output for D/A converter and digital audio transmitter.
39
[LRWDKN
|
О
|
DAC
мога
clock
output
for
left-mix
and
right-mix.
40
DAC
word
clock
output
for
individual
2
and
3.
41
101WDKN
О
|
DAC
word
clock
output
for
individual
0
and
1.
42
BTCK
©
|
Data
catch
clock
output
for
DAC
and
digital
audio
transmitter.
Word
clock
output
for
digital
audio
transmitter.
46-53,63-70
А23-А0
О
|
Address
outputs
for
the
wave
memory
(RAM/ROM).
72-74,76-80
ZIN
|
|
test
pin
for
tri-state
test.
(Connect
to
Vdd
in
normal
condition.
|
ТАО-ТАЗ
|
|
|
Input
pin for
the
function
test.
(Connect
to
the
Vss
in
normal
condition.)
Column
address
strobe
output
for
the
wave
memory
(RAM)
(low
active).
Row
address
strobe
output
for
the
wave
memory
(RAM)
(low
active).
Output
enable
out
for
the
wave
memory.
(low
active
Read/write output for the wave memory. (low active)
Chip enable output for the wave memory (ROM). (low active)
Output pin for parametric test. (Open in norma! condition.
Input pin for the function test.
Data bus for the wave memory.
б
System clock input (768 times of the sampling-rate).
ШИ Serial data input for the second LSI
| О | Serial data output for the second LSI
| О | Sync signal output for the second LSI.
О | System reset output for the second LSI.
| О | System clock output for the second LSI.