Alpine CDM-7859RB - Page 59

_ CDA-7873R
1/0 Terminal Description
Laser ON signa! output terminal. H:0N
jo |
Ee No connect terminal.
=
| - |
ID connect terminal for analog circuit.
AVSS3
Power supply terminal for analog circuit.
Focus Balance adjustment output terminal.
Tracking Balance adjustment output terminal.
Focus Error signal input terminal. (Analog input)
| 0
Ee
ae
= | connect terminal.
he
|
Tracking Error signal input terminal. (Analog input)
No connect terminal.
FBAL
TBAL
| RFENV RF Envelope signal input terminal. (Analog input)
P_weer | _1_|VREF input termina
rane | 1 [RF signe! input terminal. (for OSL)
| rt [Bias terminal for ost.
| SLE. =| 1/0 [Roop Filter terminal for DSL.
| REF | [Reference current input terminal.
[pir | 170 |Roop Filter terminal for PLL.
| puF2.——s| 1/0 [Characteristic Roop Filter switching terminal for PLL.
TRD
FOD
TOFS
AVDD2
VSS2
VCOF | 1/0 |Roop Filter terminal for VCO.
VCOF2 1/0 {Digital Servo Processor (33. 8688MHz)/Roop Filter terminal for VCO.
| 0 |Traverse compulsion sending output terminal.
| 0 |Traverse drive output terminal.
| 0 |Spindie Motor ON output terminal.
| 0. |Spindte Motor driving signal terminal. (compulsion mode output) 3-State
| 0. [Spindle Motor driving signal terminal. (Servo Error signal output)
KICK | 0 |Kick Pulse output terminal. 3-State
| 0. [Tracking Drive output terminal.
| 0. {Focus Drive output terminal.
| 0. [Tracking Offset adjustment output terminal.
| - [Power supply terminal for analog circuit (DSL,PLL,AD and DA block).
| - |GND connect terminal for analog circuit (DSL,PLL,AD and DA block).
fs
ES
| oe
ae ae
v7 | tors
| Ave
No connect terminal.
| mwas | o | PLL Samo| ing Clock output terminal. (fPCK=4. 321 8MHz)
PCK/DSLB at default:PLL Sampling Clock output/
at fulfillment command:DSL Balance output
/CLOCK Sub Code Frame Clock signal output terminal. (fCLDCK=7. 35KHz)
FCLK Crystal Frame Clock signal output terminal. (fFCLK=7.35KHz)
1PFLAG Interpolation Flag signal output terminal. H: Interpolation
aS
)
TEST2 (GND
GND connect termina! for digital circuit.
> w iw Ww f & nN = —_
a ow
n
E
post
Flag signal output terminal.
Track Cross signal input terminal.
Serial Data output termina! for monitor signal.
(SENCE, NFLOCK, NTLOCK::-etc. )
Load signal output terminal for monitor signal.
Bit Clock signal output terminal for monitor signal. (fSMCK=4.2336MHz)
GND connect terminal.
ae GND connect terminal.