AD9854
Rev. E | Page 35 of 52
A<5:0>
D<7:0>
A1
D1
A2
D2
A3
D3
t
RDHOZ
t
RDLOV
t
AHD
t
ADV
SPECIFICATION
VALUE DESCRIPTION
t
ADV
t
AHD
t
RDLOV
t
RDHOZ
15ns
5ns
15ns
10ns
ADDRESS TO DATA VALID TIME (MAXIMUM)
ADDRESS HOLD TIME TO RD SIGNAL INACTIVE (MINIMUM)
RD LOW TO OUTPUT VALID (MAXIMUM)
RD HIGH TO DATA THREE-STATE (MAXIMUM)
RD
00636-052
Figure 52. Parallel Port Read Timing Diagram
D<7:0> D1 D2 D3
SPECIFICATION
VALUE DESCRIPTION
t
ASU
t
DSU
t
ADH
t
DHD
8.0ns
3.0ns
ADDRESS SETUP TIME TO WR SIGNAL ACTIVE
DATA SETUP TIME TO WR SIGNAL ACTIVE
0ns
0ns
ADDRESS HOLD TIME TO WR SIGNAL INACTIVE
DATA HOLD TIME TO WR SIGNAL INACTIVE
t
WRLOW
t
WRHIGH
t
WR
2.5ns
WR SIGNAL MINIMUM LOW TIME
7ns
10.5ns
WR SIGNAL MINIMUM HIGH TIME
MINIMUM WRITE TIME
<5:0> A1 A2 A3
t
ASU
t
AHD
t
WRHIGH
t
WRLOW
t
DHD
t
DSU
t
WR
WR
0636-053
Figure 53. Parallel Port Write Timing Diagram