Apple Lisa - Memory Bus Timing

Confidential
Lisa Hardware Reference Manual
7-Jul-81,
MEMORY BUS TIMING
Video Cycle CPU Cycle
o
1
2 3
456
7 0
2
3 4
5
6 7
o
DotCk
CPUCk 110....._....1
L
______________________ ~r
DTACK (RAML..' _.....I
RAM --V
Addresses --" Vid Row AdcI,X,- __ V_id_Co_1 A_d_d' ___ --'X
CPu
ROWAdd'X,-_~ __ C.;.PU.;;..;;C.;.OI.;..A.;.dd;...' _____ C
-
CAS
.J
------_ ... 1
Data Out
to RAM
Valid
~~~ ________ v_al_id ____________ __
Data In ... ___ v_a_lid _____ ~
from RAM
Enci of Previous i
CPU Cycle
--1
50nS
r-
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