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Apple Lisa User Manual

Apple Lisa
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LISA
Hardware
REFERENCE
MANUAL
Bill Schottstaedt
Ext. 2379
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Apple Lisa Specifications

General IconGeneral
Release Year1983
Release DateJanuary 19, 1983
ProcessorMotorola 68000
CPU Speed5 MHz
RAM1 MB
Operating SystemLisa OS
Storage5 MB ProFile hard drive
Display12-inch monochrome
Portsone parallel port
Weight48 lbs (21.8 kg)
Dimensions15.2 x 18.7 x 13.8 inches

Summary

Overview of LISA Hardware

The Processor

Details the Motorola MC68000 microprocessor, its clock speed, and memory cycle time.

Video Display

Describes the bit-mapped display resolution and refresh mechanism.

Memory

Explains the memory management unit, address spaces, and RAM capacity.

The System Bus

Covers the system bus connections, cycle, and timing.

The CPU Board

The 68000

Details the 16-bit microprocessor, its registers, and addressing capabilities.

Interrupts

Explains the interrupt handling structure, vector table, and priority levels.

Memory Configurations

Details RAM chip configurations and board capacities.

The Memory Management Unit

Explains MMU function in address translation, access controls, and segmentation.

Segment Origin

Describes the Segment Origin Register (SORG) for physical address calculation.

Context Selection

Explains context bits for switching MMU register sets.

Segment Limit

Details the Segment Limit Register for address space checks and access control.

Process Stack

Explains how the 68000 uses the stack pointer and segment growth.

Loading the MMU Registers

Describes the procedure for initializing MMU registers via the SETUP bit.

Memory Errors

Explains detection of hard and soft memory errors and their disabling.

Status Register

Details bits for reading system bus status, errors, and video signals.

Memory Error Address Latch

Describes the latch that stores the address of memory errors.

Memory Diagnostic Mode

Explains flip-flops for testing error detection and correction circuitry.

Video Circuit

Covers display dimensions, dot clock, line frequency, and aspect ratios.

Contrast Control

Explains controlling CRT display contrast via a digital-to-analog converter.

System Bus Timing

Illustrates timing diagrams for system bus read/write cycles.

Memory Bus Timing

Shows timing diagrams for video and CPU cycles on the memory bus.

The IO Board

Input/Output Board Overview

Lists I/O devices on the board: keyboard, serial, disk, speaker.

Keyboard Interface

Describes the COPS microprocessors used for keyboard communication.

Keyboard

Details keyboard connection, scanning, N-key rollover, and FIFO buffer.

Keycodes

Explains the format and meaning of keycode bytes.

Mouse

Describes the mouse as an input device and its connector pinout.

Mouse Commands

Explains the command format for mouse interrupt configuration.

Mouse Data

Details the three-byte data format for mouse movement and button status.

Clock/Calendar Circuit

Explains the clock/calendar function, alarm capabilities, and communication.

CVSD and Speaker

Describes the CVSD circuit for audio conversion and volume control.

Serial Interfaces

Details the two built-in RS232-C serial ports and NEC 7201 interface.

Baud Rate Generation

Explains standard and 6522-controlled baud rates for serial communication.

Floppy Disk Controller

Describes the 6505 microcomputer-based disk controller.

Disk Controller Commands

Lists commands for the floppy disk controller, including RWTS.

Execute RWTS Command

Explains the command for executing Read/Write/Track/Sector routines.

Disk Data Storage

Details data storage format, block size, and disk capacity.

Non-Volatile Memory

Describes the 1K RAM backed by battery for parameter storage.

Battery

Explains the battery backup charging control and duration.

The Expansion I/O Slots

Signal Description

Describes the basic operation of bus interface signals for expansion cards.

Device Protocol

Details protocols for I/O card identification and boot ROM.

Direct Memory Access

Explains the DMA scheme, prioritization, and controller simulation.

Glossary

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