Apple Lisa - Memory Error Address Latch; Memory Diagnostic Mode

Confidential
Lisa Hardware Reference Manual 7-Jul-81
6 Serial Number Data The serial number is stored in the video
state PROM as a 56 bit number. It can be
read one bit at a time at this location:
The serial number is delivered one bit
every four CPU clock cycles, so a program
that does consecutive memory cycles at the
maximum rate can read one bit per cycle.
7 Serial Number Sync The serial number read out into bit 6 is
8-15
THE MEMORY ERROR ADDRESS LATCH
synchronized to start when the Serial Number
Sync bit is 1. The following 224 CPU
clock cycles shift out all 56 bits of the
serial number.
Unused
The memory error address latch can be read to determine the address at
which a detected hard or soft error occurred. If the status register's
hard or soft error bits are not set, the address latch contains an
indeterminate value. Once the error logging program has read the
latch, the latch is reset to permit detection of subsequent errors.
At the same time the soft error bits, the bus timeout bit, and the
vertical retrace bit are reset. The address latch reset signal
also gates the latched address data onto the data bus, so all the
status bits are reset when the error latch is read. ~1?-~ .. 4tched.
address is a physical address. The error address latch is located
at $OOFOOO in Ilo space. To reset the hard error bit, use the hard
error mask bit.
MEMORY DIAGNOSTIC MODE
Two flip-flops are prOVided to help test the error detection and
correction circuitry. DIAG! asserts the Soft Error line, and DL\G2
asserts the Hard Error line. DIAGl is set by a read or write to
$00E002 in Ilo space, and reset by a read or write to $OOEOOO.
DIAG2 is set by a read or write to $00E006 and reset by a read
or write to $00E004.
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