Apple Lisa - Direct Memory Access

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Lisa Hardware Reference Manual
The byte count is a 16 bit female byte sex number that'indicates the
length in bytes of the boot program data. The boot program is stored"
as bytes, but is read into main memory as 16 bit female words. ·The 2
byte checksum should produce a 0 (for all 16 bits) when it is added
to all the rest of the data in ROM, including the type code and the
byte count. .
If the card returns a type code of $FFFF, the boot ROM responds as if
there were no device in the slot. This code is provided for devices
that do not contain a boot program during the hardware development
phase. All production cards, however, must be self-identifying.
Since addressing is done through the SLn decode, the expansion device
boot ROM cannot be larger than 2048 bytes. Smaller ROMs can be used.
DIRECT MEMORY ACCESS
The DMA scheme provided by the Lisa is a slight modification of the
system provided by the 68000 alone. Since the BG lines are daisy
chained, the prioritization of DMA transfers is left up to the design
of the expansion I/O cards and the location of the cards. The
hardwired priority for DMA devices is:
Highest Priority
Lowest Priority
Slot 2
Slot 1
Slot 0
To insur~ that the daisy chain is not broken, any card that does not
use DMA should tie BG In to BG Out. The higher priority device
should not propogate the BG signal to lower priority devices until it
has finished using the bus. To insure proper propogation of the
daisy chained signal, it is necessary to fill the expansion slots
from right to left (from slot 2 to slot 0). Since a DMA device takes
over the bus from the 68000,. DMA transfers should be limited in time
to about 1 ms.
The DMA controller associated with the expansion device controls the
AS, ODS, LOS, and READ lines, as well as the data and address buses.
The DMA controller should simulate the 68000 control of these lines
as closely as possible. The timing on the DTACK/ signal is especially
critical. To avoid wait states in the 68000 on normal memory fetches,
the memory controller asserts DTACK/ one CPU clock cycle before the
data transfer is complete.
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7-Jul-81