Apple Lisa - Page 28

Confidential
PRj
CRDY
CR/
CBl
CB2
Lisa Hardware Reference Manual
Parity Reset (low true). PRj resets the parity latch
in the hard disk controller. It should be pulsed low
before each disk data transfer so that any parity
errors which were detected during the data transfer
can be passed on to the disk driver. If CR/ (PB7)
is high, PRJ is an input from the parallel port.
COPS Ready. This signal undergoes a high to low
transition when the COPS is ready to accept a
command (see the timing diagram below). There
is no handshake on entering a command.
Controller Reset. When CR/ is low, you can reset the
Pippin Controller connected to the hard disk port.
CBl is used to clock data transfers between the 6522
Shift Register and the CVSD circuit under the control
of T2.
CB2 is a data I/O pin between the 6S22 Shift Register
and the CVSD circuit.
COps· COMMAND TIMING
~ CRDY width -..J
------~ ~-------------
CRDY Width
TSetup
THold
Page 28
Min Max
---+------
16us
-8us
20us
20us
ISus
SOus
7-Jul-81