ASROCK B660-ITX - Page 47

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tWRRD_dg
Congure between module write to read delay.
tWRRD_dr
Congure between module write to read delay.
tWRRD_dd
Congure between module write to read delay.
tWRWR_sg
Congure between module write to write delay.
tWRWR_dg
Congure between module write to write delay.
tWRWR_dr
Congure between module write to write delay.
tWRWR_dd
Congure between module write to write delay.
Round Trip Timing
Round Trip Timing Optimization
Auto is enabled in general case.
Round Trip Level
Congure round trip level.
Initial RTL IO Delay Oset
Congure round trip latency IO delay initial oset.
Initial RTL FIF0 Delay Oset
Congure round trip latency FIF0 delay initial oset.
Initial RTL (MC0 C0 A1/A2)
Congure round trip latency initial value.
Initial RTL (MC0 C1 A1/A2)
Congure round trip latency initial value.