ASROCK H81M-VG4 R2.0 - Dram Coniguration

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DRAM Conguration
CAS# Latency (tCL)
e time between sending a column address to the memory and the beginning of the data
in response.
RAS# to CAS# Delay (tRCD)
e number of clock cycles required between the opening of a row of memory and
accessing columns within it.
Row Precharge Time (tRP)
e number of clock cycles required between the issuing of the precharge command
and opening the next row.
RAS# Active Time (tRAS)
e number of clock cycles required between a bank active command and issuing the
precharge command.
Command Rate (CR)
e delay between when a memory chip is selected and when the rst active command can
be issued.
Write Recovery Time (tWR)
e amount of delay that must elapse aer the completion of a valid write operation,
before an active bank can be precharged.