APPENDIX F
Table F-5. USART Control Register (UCR)
Bit Function
7 Clock.
0 = Use clock directly for transfer frequency (synchronous
transfer).
1 = Divide clock frequency by 16.
Register 22. Receiver Status Register (RSR). This register
contains information about serial port reception as shown in
Table F-6.
Table F-6. Receiver Status Register (RSR)
Bit Function
0 Receiver Enable Bit.
0 = Receipt disabled.
1 = Receipt enabled.
1 Synchronous Strip Enable. In synchronous mode, this bit
enables checking of whether the character in the SCR is
identical to a character in the receive buffer.
2 Match/Character in Progress. In synchronous mode, this bit
signals that a character matching the SCR byte would be
received. In asynchronous mode, this bit is set when the start
bit is detected, and cleared when the stop bit is detected.
3 Search/Break Detected. In synchronous mode, this bit signals
that a character was received that matches the SCR byte. In
asynchronous mode, this bit is set when a BREAK is received.
4 Frame Error. This bit is set when the byte received is not a
null, but the stop bit is a null.
5 Parity Error. This bit is set when the parity bit of the last
received character was incorrect.
6 Overrun Error. This bit is set when a character can't be read
into the receive buffer.
7 Buffer Full. This bit is set when a character is transferred into
the receive buffer, and cleared when it's read.
Register 23. Transmitter Status Register (TSR). This reg
ister contains information about serial port transmission (Ta
ble F-7).
Table F-7. Transmitter Status Register (TSR)
Bit Function
0 Transmit Enable.
0 = Transmission disabled.
1 = Transmission enabled.
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