OSC
EXF2
TF2
T2EX PIN
T2 PIN
TR2
EXEN2
C/T2 = 0
C/T2 = 1
CONTROL
RELOAD
OVERFLOW
CONTROL
TRANSITION
DETECTOR
TIMER 2
INTERRUPT
÷12
RCAP2LRCAP2H
TH2 TL2
Figure 2. Timer 2 Auto Reload Mode (DCEN = 0)
Table 4. T2MOD—Timer 2 Mode Control Register
T2MOD Address = 0C9H Reset Value = XXXX XX00B
Not Bit Addressable
——————T2OEDCEN
Bit76543210
Symbol Function
— Not implemented, reserved for future use.
T2OE Timer 2 Output Enable bit.
DCEN When set, this bit allows Timer 2 to be configured as an up/down counter.
overflow also causes the timer registers to be reloaded
with the 16-bit value in RCAP2H and RCAP2L. The values
in RCAP2H and RCAP2L are preset by software. If
EXEN2 = 1, a 16-bit reload can be triggered either by an
overflow or by a l-to-0 transition at external input T2EX.
This transition also sets the EXF2 bit. Both the TF2 and
EXF2 bits can generate an interrupt if enabled.
Setting the DCEN bit enables Timer 2 to count up or down,
as shown in Figure 3. In this mode, the T2EX pin controls
the direction of the count. A logic 1 at T2EX makes Timer
2 count up. The timer will overflow at 0FFFFH and set the
TF2 bit. This overflow also causes the 16-bit value in
RCAP2H and RCAP2L to be reloaded into the timer regis-
ters, TH2 and TL2, respectively.
A logic 0 at T2EX makes Timer 2 count down. The timer
underflows when TH2 and TL2 equal the values stored in
RCAP2H and RCAP2L. The underflow sets the TF2 bit
and causes 0FFFFH to be reloaded into the timer regis-
ters.
The EXF2 bit toggles whenever Timer 2 overflows or un-
derflows and can be used as a 17th bit of resolution. In this
operating mode, EXF2 does not flag an interrupt.
Auto-Reload (Up or Down Counter) (Continued)
AT89C52
7
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