Atmel AVR AT90S2323 User Manual

1
Features
• Utilizes the AVR
®
RISC Architecture
• AVR – High-performance and Low-power RISC Architecture
– 118 Powerful Instructions – Most Single Clock Cycle Execution
– 32 x 8 General-purpose Working Registers
– Up to 10 MIPS Throughput at 10 MHz
• Data and Nonvolatile Program Memory
– 2K Bytes of In-System Programmable Flash
Endurance: 1,000 Write/Erase Cycles
– 128 Bytes Internal RAM
– 128 Bytes of In-System Programmable EEPROM
Endurance: 100,000 Write/Erase Cycles
– Programming Lock for Flash Program and EEPROM Data Security
• Peripheral Features
– One 8-bit Timer/Counter with Separate Prescaler
– Programmable Watchdog Timer with On-chip Oscillator
– SPI Serial Interface for In-System Programming
• Special Microcontroller Features
– Low-power Idle and Power-down Modes
– External and Internal Interrupt Sources
– Power-on Reset Circuit
– Selectable On-chip RC Oscillator
• Specifications
– Low-power, High-speed CMOS Process Technology
– Fully Static Operation
• Power Consumption at 4 MHz, 3V, 25°C
– Active: 2.4 mA
– Idle Mode: 0.5 mA
– Power-down Mode: <1 µA
• I/O and Packages
– Three Programmable I/O Lines for AT90S/LS2323
– Five Programmable I/O Lines for AT90S/LS2343
– 8-pin PDIP and SOIC
• Operating Voltages
– 4.0 - 6.0V for AT90S2323/AT90S2343
– 2.7 - 6.0V for AT90LS2323/AT90LS2343
• Speed Grades
– 0 - 10 MHz for AT90S2323/AT90S2343-10
– 0 - 4 MHz for AT90LS2323/AT90LS2343-4
– 0 - 1 MHz for AT90LS2343-1
Pin Configuration
PDIP/SOIC
1
2
3
4
8
7
6
5
RESET
XTAL1
XTAL2
GND
VCC
PB2 (SCK/T0)
PB1 (MISO/INT0)
PB0 (MOSI)
AT90S/LS2323
1
2
3
4
8
7
6
5
RESET
(CLOCK) PB3
PB4
GND
VCC
PB2 (SCK/T0)
PB1 (MISO/INT0)
PB0 (MOSI)
AT90S/LS2343
8-bit
Microcontroller
with 2K Bytes of
In-System
Programmable
Flash
AT90S2323
AT90LS2323
AT90S2343
AT90LS2343
Rev. 1004D–09/01

Atmel AVR AT90S2323 Specifications

General

Brand	Atmel
Model	AVR AT90S2323
Category	Microcontrollers
Language	English

Summary

Pin Configuration

Clock Options

Crystal Oscillator

Use for external quartz crystal or ceramic resonator.

External Clock

Connect to XTAL1/PB3 for clock input.

Architectural Overview

General-purpose Register File

Memory Components

X, Y, and Z Registers

Address pointers for indirect data addressing.

In-System Programmable Flash

2K bytes for program storage.

EEPROM Data Memory

128 bytes for non-volatile data.

Program and Data Addressing Modes

Register Direct, Single Register Rd

Operand in register d (Rd).

Register Direct, Two Registers Rd and Rr

Operands in Rd and Rr, result in Rd.

I/O and Data Addressing Modes

I/O Direct

Operand address in 6 bits of instruction word.

Data Direct

16-bit data address in LSBs of 2-word instruction.

Data Indirect with Displacement

Address from Y/Z register plus displacement.

Reset and Interrupt Handling

Stack Pointer – SPL

Manages subroutine and interrupt stacks.

Reset Sources

Power-on, external, and watchdog reset types.

Sleep Modes

Idle Mode

Stops CPU, allows peripherals to run.

Power-down Mode

Stops oscillator, minimizes power consumption.

Timer/Counter Functionality

8-bit Timer/Counter0

Counts clock pulses or external events.

EEPROM Read/Write Access

EEPROM Address Register – EEAR

Specifies EEPROM address.

EEPROM Data Register – EEDR

Holds EEPROM data for read/write.

Prevent EEPROM Corruption

I/O Port B Overview

Alternate Functions of Port B

Describes CLOCK, SCK, MISO, MOSI functions.

Memory Programming

Fuse Bits in AT90S/LS2323

SPIEN, FSTRT bits.

Fuse Bits in AT90S/LS2343

SPIEN, RCEN bits.

Electrical Characteristics

Absolute Maximum Ratings

Stress limits for device operation.

DC Characteristics

Electrical parameters vs. voltage/temperature.

Instruction Set Summary

Packaging Information

8P3 PDIP Package

Dimensions for PDIP package.

8S2 SOIC Package

Dimensions for SOIC package.