20
AT90S/LS2323/2343
1004D–09/01
The most typical program setup for the Reset and Interrupt vector addresses are:
Reset Sources The AT90S2323/2343 provides three sources of reset:
• Power-on Reset. The MCU is reset when the supply voltage is below the Power-on
Reset threshold (V
POT
).
• External Reset. The MCU is reset when a low level is present on the RESET
pin for
more than 50 ns.
• Watchdog Reset. The MCU is reset when the Watchdog timer period expires and
the Watchdog is enabled.
During reset, all I/O registers are set to their initial values and the program starts execu-
tion from address $000. The instruction placed in address $000 must be an RJMP
(relative jump) instruction to the reset handling routine. If the program never enables an
interrupt source, the interrupt vectors are not used and regular program code can be
placed at these locations. The circuit diagram in Figure 24 shows the reset logic.
Table 4 defines the timing and electrical parameters of the reset circuitry.
Figure 24. Reset Logic
The AT90S/LS2323 has a programmable start-up time. A fuse bit (FSTRT) in the Flash
memory selects the shortest start-up time when programmed (“0”). The AT90S/LS2323
is shipped with this bit unprogrammed.
The AT90S/LS2343 has a fixed start-up time.
Address Labels Code Comments
$000 rjmp RESET ; Reset Handler
$001 rjmp EXT_INT0 ; IRQ0 Handler
$002 rjmp TIM_OVF0 ; Timer0 Overflow
; Handler;
$003 MAIN: ldi r16, low(RAMEND) ; Main program start
out SPL, r16
<instr> xxx
... ... ... ...
Power-On Reset
Circuit
Reset Circuit
Watchdog
Timer
On-Chip
RC-Oscillator
14-Stage Ripple Counter
Q0 Q13Q3
Q
QS
R
INTERNAL
RESET
POR
VCC
RESET
100 - 500K
COUNTER RESET
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