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Atmel AVR ATtiny10 Series User Manual

Atmel AVR ATtiny10 Series
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Features
Utilizes the AVR
®
RISC Architecture
High-performance and Low-power 8-bit RISC Architecture
90 Powerful Instructions – Most Single Clock Cycle Execution
32 x 8 General Purpose Working Registers
Up to 8 MIPS Throughput at 8 MHz
Nonvolatile Program and Data Memory
1K Byte of Flash Program Memory
QuickFlash
One-time Programmable (ATtiny10)
In-System Programmable (ATtiny12)
Endurance: 1,000 Write/Erase Cycles (ATtiny11/12)
64 Bytes of In-System Programmable EEPROM Data Memory (ATtiny12)
Endurance: 100,000 Write/Erase Cycles
Programming Lock for Flash Program and EEPROM Data Security
Peripheral Features
Interrupt and Wake-up on Pin Change
One 8-bit Timer/Counter with Separate Prescaler
On-chip Analog Comparator
Programmable Watchdog Timer with On-chip Oscillator
Special Microcontroller Features
Low-power Idle and Power-down Modes
External and Internal Interrupt Sources
In-System Programmable via SPI Port (ATtiny12)
Enhanced Power-on Reset Circuit (ATtiny12)
Internal Calibrated RC Oscillator (ATtiny12)
Specification
Low-power, High-speed CMOS Process Technology
Fully Static Operation
Power Consumption at 4 MHz, 3V, 25°C
Active: 2.2 mA
Idle Mode: 0.5 mA
Power-down Mode: <1 µA
Packages
8-pin PDIP and SOIC
ATtiny10 is the QuickFlash OTP Version of ATtiny11
Operating Voltages
1.8 - 5.5V (ATtiny12V-1)
2.7 - 5.5V (ATtiny11L-2 and ATtiny12L-4)
4.0 - 5.5V (ATtiny11-6 and ATtiny12-8)
Speed Grades
0 - 1 MHz (ATtiny12V-1)
0 - 2 MHz (ATtiny11L-2)
0 - 4 MHz (ATtiny12L-4)
0 - 6 MHz (ATtiny11-6)
0 - 8 MHz (ATtiny12-8)
Rev. 1006B10/99
8-bit
Microcontroller
with 1K Bytes
Flash
ATtiny10
ATtiny11
ATtiny12
Preliminary
Pin Configuration
1
2
3
4
8
7
6
5
(RESET) PB5
(XTAL1) PB3
(XTAL2) PB4
GND
VCC
PB2 (T0)
PB1 (INT0/AIN1)
PB0 (AIN0)
ATtiny10/11
PDIP/SOIC
1
2
3
4
8
7
6
5
(RESET) PB5
(XTAL1) PB3
(XTAL2) PB4
GND
VCC
PB2 (SCK/T0)
PB1 (MISO/INT0/AIN1)
PB0 (MOSI/AIN0)
ATtiny12
PDIP/SOIC
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Atmel AVR ATtiny10 Series Specifications

General IconGeneral
BrandAtmel
ModelAVR ATtiny10 Series
CategoryMicrocontrollers
LanguageEnglish

Summary

Features

Utilizes the AVR RISC Architecture

Core architecture, instruction set, and performance metrics of the AVR RISC.

Architectural Overview

Register File and ALU

Structure of CPU registers and the Arithmetic Logic Unit.

Reset and Interrupt Handling

Reset Sources

Details on Power-on, External, Watchdog, and Brown-out resets.

Interrupt Handling

Mechanisms for handling interrupts and interrupt control registers.

Sleep Modes

Sleep Modes for ATtiny10/11

Idle and Power-down modes for ATtiny10/11.

Sleep Modes for ATtiny12

Idle and Power-down modes for ATtiny12.

Watchdog Timer

Watchdog Timer Control Register – WDTCR

Register for configuring the watchdog timer's behavior.

Analog Comparator

Analog Comparator Control and Status Register – ACSR

Configuration and status bits for the analog comparator.

Memory Programming

Serial Programming

High-voltage Serial Programming

Procedure for programming via high-voltage serial interface.

Low-voltage Serial Downloading (ATtiny12 only)

Procedure for programming via low-voltage SPI interface.

Electrical Characteristics

DC Characteristics – Preliminary Data

Detailed electrical parameters like voltage, current, and timing.

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