ATtiny10/11/12
32
Watchdog Timer Control Register – WDTCR
•
Bits 7..5 - Res: Reserved bits
These bits are reserved bits in the ATtiny10/11/12 and will always read as zero.
•
Bit 4 - WDTOE: Watchdog Turn-off Enable
This bit must be set (one) when the WDE bit is cleared. Otherwise, the watchdog will not be disabled. Once set, hardware
will clear this bit to zero after four clock cycles. Refer to the description of the WDE bit for a watchdog disable procedure.
•
Bit 3 - WDE: Watchdog Enable
When the WDE is set (one) the Watchdog Timer is enabled, and if the WDE is cleared (zero) the Watchdog Timer function
is disabled. WDE can be cleared only when the WDTOE bit is set(one). To disable an enabled watchdog timer, the
following procedure must be followed:
1. In the same operation, write a logical one to WDTOE and WDE. A logical one must be written to WDE even though
it is set to one before the disable operation starts.
2. Within the next four clock cycles, write a logical 0 to WDE. This disables the watchdog.
•
Bits 2..0 - WDP2, WDP1, WDP0: Watchdog Timer Prescaler 2, 1 and 0
The WDP2, WDP1 and WDP0 bits determine the Watchdog Timer prescaling when the Watchdog Timer is enabled. The
different prescaling values and their corresponding time-out periods are shown in Table 16.
Note: The frequency of the Watchdog Oscillator is voltage dependent as shown in the section “ATtiny11 Typical Characteristics” on
page 54.
The WDR – Watchdog Reset – instruction should always be executed before the Watchdog Timer is enabled. This ensures that
the reset period will be in accordance with the Watchdog Timer prescale settings. If the Watchdog Timer is enabled without
reset, the Watchdog Timer may not start counting from zero.
Bit 76543210
$21 - - - WDTOE WDE WDP2 WDP1 WDP0 WDTCR
Read/Write R R R R/W R/W R/W R/W R/W
Initial value 0 0 0 0 0 0 0 0
Table 16. Watchdog Timer Prescale Select
WDP2 WDP1 WDP0
Number of WDT
Oscillator cycles
Typical Time-out
at V
CC
= 2.0V
Typical Time-out
at V
CC
= 3.0V
Typical Time-out
at V
CC
= 5.0V
0 0 0 16K cycles 0.15s 47 ms 15 ms
0 0 1 32K cycles 0.30s 94 ms 30 ms
0 1 0 64K cycles 0.60s 0.19 s 60 ms
0 1 1 128K cycles 1.2s 0.38 s 0.12 s
1 0 0 256K cycles 2.4s 0.75 s 0.24 s
1 0 1 512K cycles 4.8s 1.5 s 0.49 s
1 1 0 1,024K cycles 9.6s 3.0 s 0.97 s
1 1 1 2,048K cycles 19s 6.0 s 1.9 s
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