Atmel AVR User Manual

AVR Microcontrollers
AVR Instruction Set Manual
OTHER
Instruction Set Nomenclature
Status Register (SREG)
SREG Status Register
C Carry Flag
Z Zero Flag
N Negative Flag
V Two’s complement overflow indicator
S N ⊕ V, for signed tests
H Half Carry Flag
T Transfer bit used by BLD and BST instructions
I Global Interrupt Enable/Disable Flag
Registers and Operands
Rd: Destination (and source) register in the Register File
Rr: Source register in the Register File
R: Result after instruction is executed
K: Constant data
k: Constant address
b: Bit in the Register File or I/O Register (3-bit)
s: Bit in the Status Register (3-bit)
X,Y,Z: Indirect Address Register (X=R27:R26, Y=R29:R28, and
Z=R31:R30)
A: I/O location address
q: Displacement for direct addressing (6-bit)
Atmel-0856L-AVR-Instruction-Set-Manual_Other-11/2016

Atmel AVR Specifications

General

Architecture	8-bit RISC
SRAM	Up to 16 KB
Clock Speed	Up to 20 MHz
Operating Voltage	1.8V to 5.5V
ADC	10-bit ADC
Communication Interfaces	SPI, I2C, USB
Packages	DIP, SOIC, QFN
Special Features	Watchdog Timer
Flash Memory	1KB to 256KB
EEPROM	64B to 4KB

Summary

Instruction Set Nomenclature

Status Register (SREG)

Defines the bits and their meaning within the AVR Status Register (SREG).

Registers and Operands

Lists and describes common registers and operand notations used in AVR instructions.

1. I/O Registers

1.1. RAMPX, RAMPY, and RAMPZ

Registers extending address space for indirect addressing beyond 64KB.

1.2. RAMPD

Register extending address space for direct addressing beyond 64KB.

1.3. EIND

Register extending address space for indirect jumps/calls beyond 64K words.

1.4. Stack

Defines the stack for return addresses and pushed registers, including the Stack Pointer (SP).

1.5. Flags

Explains symbols used to denote flag status (affected, cleared, set, not affected).

2. The Program and Data Addressing Modes

2.1. Register Direct, Single Register Rd

Describes addressing data directly using a single register (Rd) as the operand.

2.2. Register Direct - Two Registers, Rd and Rr

Describes addressing data using two registers (Rd and Rr) as operands.

2.3. I/O Direct

Describes accessing I/O registers using a direct address from the instruction.

2.4. Data Direct

Describes accessing data memory using a direct 16-bit address.

2.5. Data Indirect with Displacement

Describes accessing data using an address formed by a register and a displacement.

2.6. Data Indirect

Describes accessing data using the contents of an address register (X, Y, or Z).

2.7. Data Indirect with Pre-decrement

Describes accessing data after decrementing the address register.

2.8. Data Indirect with Post-increment

Describes accessing data after incrementing the address register.

2.9. Program Memory Constant Addressing using the LPM, ELPM, and SPM Instructions

Describes accessing constants from program memory using LPM, ELPM, and SPM.

2.10. Program Memory with Post-increment using the LPM Z+ and ELPM Z+ Instruction

Describes accessing program memory constants with post-incremented Z register.

2.11. Direct Program Addressing, JMP and CALL

Describes accessing program memory using a direct address for jumps and calls.

2.12. Indirect Program Addressing, IJMP and ICALL

Describes accessing program memory using the Z register for jumps and calls.

2.13. Relative Program Addressing, RJMP and RCALL

Describes accessing program memory using PC-relative addressing for jumps and calls.

3. Conditional Branch Summary

Test

Summarizes conditional branch instructions based on status register flags.

Boolean

Shows the Boolean logic for each conditional branch test.

Mnemonic

Lists the mnemonics for conditional branch instructions.

Complementary Boolean

Lists the complementary Boolean logic for conditional branches.

Mnemonic

Lists the mnemonics for complementary conditional branches.

Comment

Provides notes on signed/unsigned comparisons for branches.

4. Instruction Set Summary

Table 4-1. Versions of AVR 8-bit CPU

Lists different AVR CPU versions and their key features/differences.

Table 4-2. Arithmetic and Logic Instructions

Summarizes arithmetic and logic instructions with mnemonics, flags, and clock cycles.

Table 4-3. Branch Instructions

Summarizes branch instructions with mnemonics, flags, and clock cycles.

Table 4-4. Data Transfer Instructions

Summarizes data transfer instructions with mnemonics, flags, and clock cycles.

Table 4-5. Bit and Bit-test Instructions

Summarizes bit manipulation and testing instructions.

Table 4-6. MCU Control Instructions

Summarizes microcontroller control instructions like NOP, SLEEP, WDR, BREAK.

5. ADC – Add with Carry

5.1. Description

Adds two registers and the C flag, storing the result in Rd.

5.2. Status Register (SREG) and Boolean Formula

Details how ADC affects SREG flags and provides Boolean formulas.

6. ADD – Add without Carry

6.1. Description

Adds two registers, storing the result in Rd, without affecting the C flag.

6.2. Status Register (SREG) and Boolean Formula

Details how ADD affects SREG flags and provides Boolean formulas.

8. AND – Logical AND

8.1. Description

Performs logical AND between Rd and Rr, storing the result in Rd.

8.2. Status Register (SREG) and Boolean Formula

Details how AND affects SREG flags and provides Boolean formulas.

9. ANDI – Logical AND with Immediate

9.1. Description

Performs logical AND between Rd and an immediate value, storing the result in Rd.

9.2. Status Register (SREG) and Boolean Formula

Details how ANDI affects SREG flags and provides Boolean formulas.

10. ASR – Arithmetic Shift Right

10.1. Description

Shifts bits right in Rd, preserving the sign bit.

10.2. Status Register (SREG) and Boolean Formula

Details how ASR affects SREG flags and provides Boolean formulas.

13. BRBC – Branch if Bit in SREG is Cleared

13.1. Description

Branches if a specified bit in SREG is cleared.

13.2. Status Register (SREG) and Boolean Formula

Details how BRBC affects SREG flags (none affected).

18. BREQ – Branch if Equal

18.1. Description

Branches if the Zero flag (Z) is set (result of comparison was equal).

18.2. Status Register (SREG) and Boolean Formula

Details how BREQ affects SREG flags (none affected).

24. BRLO – Branch if Lower (Unsigned)

24.1. Description

Branches if unsigned comparison result is lower (Carry flag set).

24.2. Status Register (SREG) and Boolean Formula

Details how BRLO affects SREG flags (none affected).

25. BRLT – Branch if Less Than (Signed)

25.1. Description

Branches if signed comparison result is less than (N XOR V is set).

25.2. Status Register (SREG) and Boolean Formula

Details how BRLT affects SREG flags (none affected).

36. CALL – Long Call to a Subroutine

36.1. Description

Calls a subroutine at any address in program memory, saving return address.

36.2. Status Register (SREG) and Boolean Formula

Details how CALL affects SREG flags (none affected).

39. CLC – Clear Carry Flag

39.1. Description

Clears the Carry flag (C) in SREG.

39.2. Status Register (SREG) and Boolean Formula

Details how CLC affects SREG flags (only C flag).

43. CLR – Clear Register

43.1. Description

Clears all bits in a register by XORing it with itself.

43.2. Status Register (SREG) and Boolean Formula

Details how CLR affects SREG flags (Z is set, others unaffected).

49. CP – Compare

49.1. Description

Compares two registers (Rd and Rr) without changing their values.

49.2. Status Register (SREG) and Boolean Formula

Details how CP affects SREG flags and provides Boolean formulas.

51. CPI – Compare with Immediate

51.1. Description

Compares a register (Rd) with an immediate value.

51.2. Status Register (SREG) and Boolean Formula

Details how CPI affects SREG flags and provides Boolean formulas.

53. DEC – Decrement

53.1. Description

Subtracts 1 from a register (Rd).

53.2. Status Register (SREG) and Boolean Formula

Details how DEC affects SREG flags and provides Boolean formulas.

58. EOR – Exclusive OR

58.1. Description

Performs logical XOR between Rd and Rr, storing the result in Rd.

58.2. Status Register (SREG) and Boolean Formula

Details how EOR affects SREG flags and provides Boolean formulas.

64. IN - Load an I/O Location to Register

64.1. Description

Loads data from an I/O location into a register.

64.2. Status Register (SREG) and Boolean Formula

Details how IN affects SREG flags (none affected).

65. INC – Increment

65.1. Description

Adds 1 to a register (Rd).

65.2. Status Register (SREG) and Boolean Formula

Details how INC affects SREG flags and provides Boolean formulas.

70. LD – Load Indirect from Data Space to Register using Index X

70.1. Description

Loads byte indirectly from data space using X pointer.

70.2. Status Register (SREG) and Boolean Formula

Details how LD affects SREG flags (none affected).

71. LD (LDD) – Load Indirect from Data Space to Register using Index Y

71.1. Description

Loads byte indirectly from data space using Y pointer.

71.2. Status Register (SREG) and Boolean Formula

Details how LD (LDD) affects SREG flags (none affected).

72. LD (LDD) – Load Indirect From Data Space to Register using Index Z

72.1. Description

Loads byte indirectly from data space using Z pointer.

72.2. Status Register (SREG) and Boolean Formula

Details how LD (LDD) affects SREG flags (none affected).

73. LDI – Load Immediate

73.1. Description

Loads an 8-bit constant into a register (16-31).

73.2. Status Register (SREG) and Boolean Formula

Details how LDI affects SREG flags (none affected).

76. LPM – Load Program Memory

76.1. Description

Loads a byte from program memory using Z pointer.

76.2. Status Register (SREG) and Boolean Formula

Details how LPM affects SREG flags (none affected).

77. LSL – Logical Shift Left

77.1. Description

Shifts bits left in Rd, clearing bit 0 and loading bit 7 into C flag.

77.2. Status Register (SREG) and Boolean Formula

Details how LSL affects SREG flags and provides Boolean formulas.

78. LSR – Logical Shift Right

78.1. Description

Shifts bits right in Rd, clearing bit 7 and loading bit 0 into C flag.

78.2. Status Register (SREG) and Boolean Formula

Details how LSR affects SREG flags and provides Boolean formulas.

79. MOV – Copy Register

79.1. Description

Copies the content of one register (Rr) to another (Rd).

79.2. Status Register (SREG) and Boolean Formula

Details how MOV affects SREG flags (none affected).

81. MUL – Multiply Unsigned

81.1. Description

Performs 8-bit x 8-bit unsigned multiplication, result in R1:R0.

81.2. Status Register (SREG) and Boolean Formula

Details how MUL affects SREG flags and provides Boolean formulas.

82. MULS – Multiply Signed

82.1. Description

Performs 8-bit x 8-bit signed multiplication, result in R1:R0.

82.2. Status Register (SREG) and Boolean Formula

Details how MULS affects SREG flags and provides Boolean formulas.

84. NEG – Two’s Complement

84.1. Description

Replaces register Rd with its two's complement.

84.2. Status Register (SREG) and Boolean Formula

Details how NEG affects SREG flags and provides Boolean formulas.

86. OR – Logical OR

86.1. Description

Performs logical OR between Rd and Rr, storing the result in Rd.

86.2. Status Register (SREG) and Boolean Formula

Details how OR affects SREG flags and provides Boolean formulas.

88. OUT – Store Register to I/O Location

88.1. Description

Stores data from a register (Rr) to an I/O location.

88.2. Status Register (SREG) and Boolean Formula

Details how OUT affects SREG flags (none affected).

89. POP – Pop Register from Stack

89.1. Description

Loads a register (Rd) from the stack, incrementing the Stack Pointer.

89.2. Status Register (SREG) and Boolean Formula

Details how POP affects SREG flags (none affected).

90. PUSH – Push Register on Stack

90.1. Description

Stores a register (Rr) onto the stack, decrementing the Stack Pointer.

90.2. Status Register (SREG) and Boolean Formula

Details how PUSH affects SREG flags (none affected).

91. RCALL – Relative Call to Subroutine

91.1. Description

Calls a subroutine at a relative address within PC range.

91.2. Status Register (SREG) and Boolean Formula

Details how RCALL affects SREG flags (none affected).

92. RET – Return from Subroutine

92.1. Description

Returns from a subroutine by loading address from stack.

92.2. Status Register (SREG) and Boolean Formula

Details how RET affects SREG flags (none affected).

93. RETI – Return from Interrupt

93.1. Description

Returns from an interrupt routine, setting the Global Interrupt flag.

93.2. Status Register (SREG) and Boolean Formula

Details how RETI affects SREG flags (I flag set).

94. RJMP – Relative Jump

94.1. Description

Jumps to a relative address within PC range.

94.2. Status Register (SREG) and Boolean Formula

Details how RJMP affects SREG flags (none affected).

95. ROL – Rotate Left trough Carry

95.1. Description

Rotates bits left in Rd, with carry shifting into bit 0 and bit 7 into C flag.

95.2. Status Register (SREG) and Boolean Formula

Details how ROL affects SREG flags and provides Boolean formulas.

97. SBC – Subtract with Carry

97.1. Description

Subtracts two registers and the C flag, storing the result in Rd.

97.2. Status Register (SREG) and Boolean Formula

Details how SBC affects SREG flags and provides Boolean formulas.

98. SBCI – Subtract Immediate with Carry

98.1. Description

Subtracts an immediate value and the C flag from a register.

98.2. Status Register (SREG) and Boolean Formula

Details how SBCI affects SREG flags and provides Boolean formulas.

99. SBI – Set Bit in I/O Register

99.1. Description

Sets a specified bit in an I/O register.

99.2. Status Register (SREG) and Boolean Formula

Details how SBI affects SREG flags (none affected).

100. SBIC – Skip if Bit in I/O Register is Cleared

100.1. Description

Skips next instruction if a bit in an I/O register is cleared.

100.2. Status Register (SREG) and Boolean Formula

Details how SBIC affects SREG flags (none affected).

101. SBIS – Skip if Bit in I/O Register is Set

101.1. Description

Skips next instruction if a bit in an I/O register is set.

101.2. Status Register (SREG) and Boolean Formula

Details how SBIS affects SREG flags (none affected).

102. SBIW – Subtract Immediate from Word

102.1. Description

Subtracts an immediate value from a register pair.

102.2. Status Register (SREG) and Boolean Formula

Details how SBIW affects SREG flags and provides Boolean formulas.

103. SBR – Set Bits in Register

103.1. Description

Sets specified bits in register Rd using a mask.

103.2. Status Register (SREG) and Boolean Formula

Details how SBR affects SREG flags and provides Boolean formulas.

104. SBRC – Skip if Bit in Register is Cleared

104.1. Description

Skips next instruction if a bit in a register is cleared.

104.2. Status Register (SREG) and Boolean Formula

Details how SBRC affects SREG flags (none affected).

105. SBRS – Skip if Bit in Register is Set

105.1. Description

Skips next instruction if a bit in a register is set.

105.2. Status Register (SREG) and Boolean Formula

Details how SBRS affects SREG flags (none affected).

106. SEC – Set Carry Flag

106.1. Description

Sets the Carry flag (C) in SREG.

106.2. Status Register (SREG) and Boolean Formula

Details how SEC affects SREG flags (only C flag).

107. SEH – Set Half Carry Flag

107.1. Description

Sets the Half Carry flag (H) in SREG.

107.2. Status Register (SREG) and Boolean Formula

Details how SEH affects SREG flags (only H flag).

108. SEI – Set Global Interrupt Flag

108.1. Description

Sets the Global Interrupt flag (I) in SREG, enabling interrupts.

108.2. Status Register (SREG) and Boolean Formula

Details how SEI affects SREG flags (only I flag).

109. SEN – Set Negative Flag

109.1. Description

Sets the Negative flag (N) in SREG.

109.2. Status Register (SREG) and Boolean Formula

Details how SEN affects SREG flags (only N flag).

111. SES – Set Signed Flag

111.1. Description

Sets the Signed flag (S) in SREG.

111.2. Status Register (SREG) and Boolean Formula

Details how SES affects SREG flags (only S flag).

112. SET – Set T Flag

112.1. Description

Sets the T flag in SREG.

112.2. Status Register (SREG) and Boolean Formula

Details how SET affects SREG flags (only T flag).

113. SEV – Set Overflow Flag

113.1. Description

Sets the Overflow flag (V) in SREG.

113.2. Status Register (SREG) and Boolean Formula

Details how SEV affects SREG flags (only V flag).

114. SEZ – Set Zero Flag

114.1. Description

Sets the Zero flag (Z) in SREG.

114.2. Status Register (SREG) and Boolean Formula

Details how SEZ affects SREG flags (only Z flag).

118. ST – Store Indirect From Register to Data Space using Index X

118.1. Description

Stores byte indirectly to data space using X pointer.

118.2. Status Register (SREG) and Boolean Formula

Details how ST affects SREG flags (none affected).

119. ST (STD) – Store Indirect From Register to Data Space using Index Y

119.1. Description

Stores byte indirectly to data space using Y pointer.

119.2. Status Register (SREG) and Boolean Formula

Details how ST (STD) affects SREG flags (none affected).

120. ST (STD) – Store Indirect From Register to Data Space using Index Z

120.1. Description

Stores byte indirectly to data space using Z pointer.

120.2. Status Register (SREG) and Boolean Formula

Details how ST (STD) affects SREG flags (none affected).

123. SUB – Subtract Without Carry

123.1. Description

Subtracts two registers, storing the result in Rd, without affecting C flag.

123.2. Status Register (SREG) and Boolean Formula

Details how SUB affects SREG flags and provides Boolean formulas.

124. SUBI – Subtract Immediate

124.1. Description

Subtracts an immediate value from a register, storing the result in Rd.

124.2. Status Register (SREG) and Boolean Formula

Details how SUBI affects SREG flags and provides Boolean formulas.

125. SWAP – Swap Nibbles

125.1. Description

Swaps the high and low nibbles within a register.

125.2. Status Register (SREG) and Boolean Formula

Details how SWAP affects SREG flags (none affected).

126. TST – Test for Zero or Minus

126.1. Description

Tests if a register is zero or negative via a logical AND with itself.

126.2. Status Register (SREG) and Boolean Formula

Details how TST affects SREG flags and provides Boolean formulas.

129. Datasheet Revision History

129.1. Rev.0856L - 11/2016

Complete document review and new template.

129.2. Rev.0856K - 04/2016

Note added to RETI section.

129.3. Rev.0856J - 07/2014

Corrections to Conditional Branch Summary and Description sections.

129.4. Rev.0856I – 07/2010

Updates to Instruction Set Summary and clock cycle counts.

129.5. Rev.0856H – 04/2009

Updates to Instruction Set Summary and compatibility sections.