(i) 1001 000d dddd 1100
(ii) 1001 000d dddd 1101
(iii) 1001 000d dddd 1110
70.2. Status Register (SREG) and Boolean Formula
I T H S V N Z C
– – – – – – – –
Example:
clr r27 ; Clear X high byte
ldi r26,$60 ; Set X low byte to $60
ld r0,X+ ; Load r0 with data space loc. $60(X post inc)
ld r1,X ; Load r1 with data space loc. $61
ldi r26,$63 ; Set X low byte to $63
ld r2,X ; Load r2 with data space loc. $63
ld r3,–X ; Load r3 with data space loc. $62(X pre dec)
Words 1 (2 bytes)
Cycles (i): 1
(2)
(ii): 2
(iii): 3
(2)
Cycles XMEGA (i): 1
(1)
(ii): 1
(1)
(iii): 2
(1)
1. Note:  If the LD instruction is accessing internal SRAM, one extra cycle is inserted.
2. Note:  LD instruction can load data from program memory since the flash is memory mapped.
Loading data from the data memory takes one clock cycle, and loading from the program memory
takes two clock cycles. But if an interrupt occur (before the last clock cycle) no additional clock
cycles are necessary when loading from the program memory. Hence, the instruction takes only
one clock cycle to execute.
LD instruction with pre-decrement can load data from program memory since the flash is memory
mapped. Loading data from the data memory takes two clock cycles, and loading from the program
memory takes three clock cycles. But if an interrupt occur (before the last clock cycle) no additional
clock cycles are necessary when loading from the program memory. Hence, the instruction takes
only one clock cycle to execute.
Atmel AVR Instruction Set Manual [OTHER]
Atmel-0856L-AVR-Instruction-Set-Manual_Other-11/2016
108
To Next Page
Loading...
Need help?
General
