77. LSL – Logical Shift Left
77.1. Description
Shifts all bits in Rd one place to the left. Bit 0 is cleared. Bit 7 is loaded into the C Flag of the SREG. This
operation effectively multiplies signed and unsigned values by two.
Operation:
(i)
←
C
←
b7 - - - - - - - - - - - - - - - - - - b0
←
0
Syntax: Operands: Program Counter:
(i) LSL Rd 0 ≤ d ≤ 31 PC ← PC + 1
16-bit Opcode: (see ADD Rd,Rd)
0000 11dd dddd dddd
77.2. Status Register (SREG) and Boolean Formula
I T H S V N Z C
– – ⇔ ⇔ ⇔ ⇔ ⇔ ⇔
H Rd3
S N ⊕ V, for signed tests.
V N ⊕ C, for N and C after the shift.
N R7
Set if MSB of the result is set; cleared otherwise.
Z R7 • R6 • R5 • R4 • R3 • R2 • R1 • R0
Set if the result is $00; cleared otherwise.
C Rd7
Set if, before the shift, the MSB of Rd was set; cleared otherwise.
R (Result) equals Rd after the operation.
Example:
add r0,r4 ; Add r4 to r0
lsl r0 ; Multiply r0 by 2
Words 1 (2 bytes)
Atmel AVR Instruction Set Manual [OTHER]
Atmel-0856L-AVR-Instruction-Set-Manual_Other-11/2016
120
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