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Atmel AVR User Manual

Atmel AVR
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129. Datasheet Revision History
Note that the referring page numbers in this section are referred to this document. The referring revision
in this section is referred to the document revision.
129.1. Rev.0856L - 11/2016
A complete review of the document.
New document template.
129.2. Rev.0856K - 04/2016
A note has been added to section “RETI – Return from Interrupt”.
129.3. Rev.0856J - 07/2014
Section “Conditional Branch Summary” has been corrected.
2. The first table in section “Description" has been corrected.
3. “TBD” in “Example” in section "Description”" has been removed.
4. The LAC operation in section "LAC – Load and Clear" has been corrected.
5. New template has been added.
129.4. Rev.0856I – 07/2010
1. Updated section "Instruction Set Summary" with new instructions: LAC, LAS, LAT, and XCH.
Section "LAC - Load and Clear"
Section "LAS – Load and Set"
Section "LAT – Load and Toggle"
Section "XCH – Exchange"
2. Updated number of clock cycles column to include Reduced Core tinyAVR.
(ATtiny replaced by Reduced Core tinyAVR).
129.5. Rev.0856H – 04/2009
1. Updated section "Instruction Set Summary":
Updated number of clock cycles column to include Reduced Core tinyAVR.
2. Updated sections for Reduced Core tinyAVR compatibility:
Section "CBI – Clear Bit in I/O Register"
Section "LD – Load Indirect from Data Space to Register using Index X"
Section "LD (LDD) – Load Indirect from Data Space to Register using Index Y"
Section "LD (LDD) – Load Indirect From Data Space to Register using Index Z"
Atmel AVR Instruction Set Manual [OTHER]
Atmel-0856L-AVR-Instruction-Set-Manual_Other-11/2016
189

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Atmel AVR Specifications

General IconGeneral
Architecture8-bit RISC
SRAMUp to 16 KB
Clock SpeedUp to 20 MHz
Operating Voltage1.8V to 5.5V
ADC10-bit ADC
Communication InterfacesSPI, I2C, USB
PackagesDIP, SOIC, QFN
Special FeaturesWatchdog Timer
Flash Memory1KB to 256KB
EEPROM64B to 4KB

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