61. FMULSU – Fractional Multiply Signed with Unsigned
61.1. Description
This instruction performs 8-bit × 8-bit → 16-bit signed multiplication and shifts the result one bit left.
Rd Rr R1 R0
Multiplicand
×
Multiplier
→
Product High Product Low
8 8 16
Let (N.Q) denote a fractional number with N binary digits left of the radix point, and Q binary digits right of
the radix point. A multiplication between two numbers in the formats (N1.Q1) and (N2.Q2) results in the
format ((N1+N2).(Q1+Q2)). For signal processing applications, the format (1.7) is widely used for the
inputs, resulting in a (2.14) format for the product. A left shift is required for the high byte of the product to
be in the same format as the inputs. The FMULSU instruction incorporates the shift operation in the same
number of cycles as MULSU.
The (1.7) format is most commonly used with signed numbers, while FMULSU performs a multiplication
with one unsigned and one signed input. This instruction is therefore most useful for calculating two of the
partial products when performing a signed multiplication with 16-bit inputs in the (1.15) format, yielding a
result in the (1.31) format. Note: the result of the FMULSU operation may suffer from a 2's complement
overflow if interpreted as a number in the (1.15) format. The MSB of the multiplication before shifting must
be taken into account, and is found in the carry bit. See the following example.
The multiplicand Rd and the multiplier Rr are two registers containing fractional numbers where the
implicit radix point lies between bit 6 and bit 7. The multiplicand Rd is a signed fractional number, and the
multiplier Rr is an unsigned fractional number. The 16-bit signed fractional product with the implicit radix
point between bit 14 and bit 15 is placed in R1 (high byte) and R0 (low byte).
This instruction is not available in all devices. Refer to the device specific instruction set summary.
Operation:
(i) R1:R0 ← Rd × Rr (signed (1.15) ← signed (1.7) × unsigned (1.7))
Syntax: Operands: Program Counter:
(i) FMULSU Rd,Rr 16 ≤ d ≤ 23, 16 ≤ r ≤ 23 PC ← PC + 1
16-bit Opcode:
0000 0011 1ddd 1rrr
61.2. Status Register (SREG) and Boolean Formula
I T H S V N Z C
– – – – – – ⇔ ⇔
C R16
Atmel AVR Instruction Set Manual [OTHER]
Atmel-0856L-AVR-Instruction-Set-Manual_Other-11/2016
96
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