Mnemonic Operands Description Op Flags
#Clocks
AVR
#Clocks
AVRxm
#Clocks
AVRxt
#Clocks
AVRrc
SEH Set Half Carry
Flag in SREG
H ← 1 H 1 1 1 1
CLH Clear Half
Carry Flag in
SREG
H ← 0 H 1 1 1 1
Table 4-6. MCU Control Instructions
Mnemonic Operands Description Operation Flags
#Clocks
AVR
#Clocks
AVRxm
#Clocks
AVRxt
#Clocks
AVRrc
BREAK Break (See also in
Debug interface
description)
None 1 1 1 1
NOP No Operation None 1 1 1 1
SLEEP Sleep (see also power
management and
sleep description)
None 1 1 1 1
WDR Watchdog Reset (see also
Watchdog
Controller
description)
None 1 1 1 1
Note:
1. Cycle time for data memory accesses assume internal RAM access, and are not valid for accesses
through the NVM controller. A minimum of one extra cycle must be added when accessing memory
through the NVM controller (such as Flash and EEPROM), but depending on simultaneous
accesses by other masters or the NVM controller state, there may be more than one extra cycle.
2. One extra cycle must be added when accessing lower (64 bytes of) I/O space.
3. The instruction is not available on all devices.
4. Device dependent. See the device specific datasheet.
Atmel AVR Instruction Set Manual [OTHER]
Atmel-0856L-AVR-Instruction-Set-Manual_Other-11/2016
29
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