Audio Precision B Series - AMC Rear Panel I;O and Sync Specifications

88 APx PDM 16 Input Module for B Series: Specifications
PDM 16
Resolution 0.01 V
Accuracy ±0.05 V
OUTPUT CHARACTERISTICS
Output Voltage High VOH ILOAD = 0.5 mA 0.7 × VINT V
Output Voltage Low VOL ILOAD = 0.5 mA 0.3 × VINT V
Output Impedance Zo At connector pin 50 Ohms
VDD OUTPUT
DC Voltage VDD 0.0 3.60 V
Resolution 0.01 V
Accuracy ±0.05 V
Maximum Current IMAX 50 mA
TIMING CHARACTERISTICS
PDM RECEIVER
t
CLKRX
Clock period (master or slave mode) 41 7813 ns
t
HP
Data hold time, rising edge 0 ns
t
HN
Data hold time, falling edge 0 ns
t
SU
Data setup time 9 ns
PDM Input Jitter Tolerance
Sine wave jitter, bit clock rates from 128kHz
to 24.576 MHz
<= 3.5 UI (sub-
ject to 1591ns
max jitter limit)
UI
2
Notes to Specifications
1. System specification including contributions from both generator and analyzer subject to the following condition: Bit Clock  192 kHz.
2. For PDM, the Unit Interval (UI) is defined as 1/fb, where fb is the bitclock rate in hertz.
Parameter Symbol Test Conditions Min Type Max Unit