Basler A302f - Page 18

Operation and Features
3-2 BASLER A302f
DRAFT
Figure 3-1: Sensor Architecture
Figure 3-2: Block Diagram
Pixels
CCD Sensor
VGCADC
PixelsPixelsPixels
Vert.
Shift
Reg.
Vert.
Shift
Reg.
Vert.
Shift
Reg.
Vert.
Shift
Reg.
Horizontal
Shift Register
CCD
Sensor
-
A/D
Converter
FPGA
Link
Layer
Controller
Physical
Layer
Controller
Micro-
controller
1
Micro-
controller
2
Image Data
Image
Data
Isochronous
and
Asynchronous
Data
Isochronous
and
Asynchronous
Data
IEEE
1394
Bus
Asynchronous
Data
Control
Control
Control:
Shutter
Binning
AOI
Gain
Brtness.
IntEn
ExTrig
Gain &
Brightness
2 MB
SDRAM
Image
Buffer
Image
Data
Shading
Correction
Data