— 9 —
7-4. Reset circuit
The voltage fluctuation of VDD is controlled of IC10 (S-80727AN).
CPU is done Reset by pushing Reset Switch or drifting VDD.
7-5. Data communication between CPU and EEPROM IC11(BR93LC46A).
EEPROM is Rom that write / erase is possible electrically.
BR93LC46A is a non- volatile register, and serial data of 16 bit can be memorized with 64
register.
CS: Chip select
SK: Serial data clock
DI: Serial data input
DO: Serial data output
64 words X 16 bits 1,024 bits
Vdd
S-80727AN
2
3
1
Reset SW
CPU
Reset
17
CPU
EEPRom
CS
SK
DI
DO
EEPCS
AD2
AD1
AD0
1
2
3
4
36
14
15
16
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