Casio MG-500 - Page 18

(3) Address Latch
Receiving
signal
ALE
from
CPU,
signals
ADO
-
AD7
are
latched
in
and
become
lower
address
signals
AQ
-
A7.
Lotches the address bus
and keeps its status until
it recieves the next ALE signal:
Date/Address
bus
perkates
CPU provides High level
when the dato bus carries
address dato.
(4) MIDI Buffer
Amplifies the MID! output signal from CPU.
Me mo