Clevo NH77DCQ User Manual

5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
DESIGN NOTE:PEQ
Programmalbe input equalization levels;internal pull
down at~150k ,3.3v I/O
L: default, LEQ, compensate channel loss up to 12dB at
HBR2
H: HEQ, compensate channel loss up to 15dB at HBR2
M:LLEQ, compensate channel loss up to 5dB at HBR2
4/2/2018
MINI DISPLAY PORT A(PS8330B)
0715 0715
11/24/2017
PDB PIN:
L:Chip power down
H:Normal operation(default)
月
PS8330B
月 Mini DP Conn
Modify,3/19 Tim
Footprint M-SOT23-5
ᾖ㓡䁢
M-SOT23-5A
6/14 Tim
For Safety LPS.
Raven add 0809
DESIGN NOTE:CFG0
Configuration pin for automatic EQ and
Aux interception; Internal pull down at
~150Kohm,3.3V I/O
L: default, automatic EQ enable and Aux interception enable
H: automatic EQ disable and AUX interception enable
M: automatic EQ disable and AUX interception
disable,no pre-emphasis, 600mVpp sw ing
DESIGN NOTE:CFG1
Configuration pin for auto test and input offset
cancellation,3.3V IO, internal pull up at~150K
H: default, auto test disable and input offset cancellation
enable
L: auto test enable and input offset cancellation enable
M: auto test disable and input offset cancellation disable
Gary 2/18/2019
MDP_I_PWR
3.3VS
3.3VS3.3VS
3.3VS
3.3VS
3.3VS
3.3VS 3.3VS
3.3VS
MDP_I_PWR
3.3VS
3.3VS
MDP_I_PWR
5VS
5VS
3.3VS
5VS
3.3VS
3.3VS
3.3VS
3.3VS8,9,23,24,28,29,30, 31,32,33,34,35,38,39,40,42,43,44,45,47,48,52,59,70,71
5VS29,31,43,44,45, 46,47,70,71, 72
IGPU_LANE0P2
IGPU_LANE2P2
IGPU_LANE1P2
IGPU_LANE1N2
IGPU_LANE3N2
IGPU_LANE0N2
IGPU_LANE2N2
IGPU_LANE3P2
SUSB29,43,47
I_MDP_HPD34
I_MDP_CLK34
IGPU_AUX_CH_P2
IGPU_AUX_CH_N2
I_MDP_DATA34
Title
Size Document Number Rev
Date: Sheet
of
6-71-NH5D0-D02
D02
[27] mDP (iGPU)
Custom
27 74Friday, February 07, 2020
ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
SCHEMATIC1
Title
Size Document Number Rev
Date: Sheet
of
6-71-NH5D0-D02
D02
[27] mDP (iGPU)
Custom
27 74Friday, February 07, 2020
ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
SCHEMATIC1
Title
Size Document Number Rev
Date: Sheet
of
6-71-NH5D0-D02
D02
[27] mDP (iGPU)
Custom
27 74Friday, February 07, 2020
ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
SCHEMATIC1
C1141 0.1u_10V_X7R_04
C1105 0.1u_10V_X7R_04
R697
*100K_1%_04
C1140 0.1u_10V_X7R_04
C1145
220p_50V_NPO_04
C1095 0.1u_10V_X7R_04
D15
*TVUDF1004AD0
5
1
2
3
4
10
9
8
7
6
T123
C1090 0.1u_10V_X7R_04
C1096 0.1u_10V_X7R_04
C1107 0.1u_10V_X7R_04
C1089 0.1u_10V_X7R_04
S D
G
Q64A
MTDK3S6R
2
6 1
C1138 0.1u_10V_X7R_04
R691
4.99K_1%_04
C1088 2.2u_6. 3V_X5R_04
R341
*100K_04
R683*4.7K_04
R698
100K_04
C1147 0.1u_10V_X7R_04
R699
1M_04
R678*4.7K_04
D38
BAV99 RECTIFIER
A
C
AC
C1151
10u_6.3V_X5R_06
C1146 0.1u_10V_X7R_04
R687*4.7K_04
R722 1K_04
C1137 0.1u_10V_X7R_04
C1136 0.1u_10V_X7R_04
R688*4.7K_04
Q66
2SK3018S3
G
DS
S
D
G
Q67A
MTDK3S6R
2
61
R692
*100K_1%_04
C1093 0.1u_10V_X7R_04
R682*4.7K_04
D17
*TVUDF1004AD0
5
1
2
3
4
10
9
8
7
6
PS8330B
U44
PS8330B
VDD33
1
CEXT
2
I2C_ADDR
3
SCL_CTLPEQ
4
SDA_CLTCFG0
5
VDD33
6
REXT
7
CAD_SRC
8
HPD_SRC
9
CAD_SNK
10
HPD_SNK
11
VDD33
12
OUT3n
13
OUT3p
14
NC
15
OUT2n
16
OOUT2p
17
GND
18
OUT1n
19
OUT1p
20
NC
21
OUT0n
22
OUT0p
23
GND
24
VDD33
36
RST#
35
SDA_DDC
34
SCL_DDC
33
VDD33
32
GND
31
AUX_SRCp
30
AUX_SRCn
29
AUX_SNKp
28
AUX_SNKn
27
PD#
26
VDD33
25
IN3n
48
IN3p
47
NC
46
IN2n
45
IN2p
44
NC
43
IN1n
42
IN1p
41
CFG1
40
IN0n
39
IN0p
38
NC
37
EPAD
49
R704
100K_1%_04
C1139 0.1u_10V_X7R_04
S D
G
Q65B
MTDK3S6R
5
34
S D
G
Q64B
MTDK3S6R
5
34
C1124
0.01u_16V_X7R_04
R675*4.7K_04
12
20
13
15
10
8
4
3
16
2
6
14
18
1
5
7
9
11
19
17
COMMON
C17737-120A9-L
J_MDP1
PCB Footprint = c-909jd20fstc 6-1
P/N = 6-21-11Y20-020
1
GND
2
HPD
3
LANE_0P
4
CONFIG1
5
LANE_0N
6
CONFIG2
7
GND
8
GND
9
LANE_1P
10
LANE_3P
11
LANE_1N
12
LANE_3N
13
GND
14
GND
15
LANE_2P
16
AUX_CHP
17
LANE_2N
18
AUX_CHN
19
GND
20
PWR
GND4
SHIELD6
GND3
SHIELD5
GND2
SHIELD2
GND1
SHIELD1
R677
100K_04
S
D
G
Q67B
MTDK3S6R
5
34
R705
100K_04
C1103 2.2u_6.3V_X5R_04
U47
SY6288D20AAC
PCB Footprint = M-SOT23-5A
VOUT
1
VIN
5
GND
2
EN#
4
OC#
3
S D
G
Q65A
MTDK3S6R
2
61
C765
10u_6.3V_X5R_06
C1091 0.1u_10V_X7R_04
R685 10K_04
R708
100K_1%_04
C1092 0.1u_10V_X7R_04
C1094 0.1u_10V_X7R_04
C1086
0.1u_6.3V_X5R_02
I_MDP_D2J
I_MDP_D#2J
I_MDP_D3J
I_MDP_D#3J
I_MDP_D1J
I_MDP_HPD_R
I_MDP_D#0J
I_MDP_AUX#_R
I_MDP_AUX_R
I_MDP_MODE
I_MDP_D#1J
I_MDP_D0J
I_MDPC_CEC
I_MDP_D#2JI_MDP_D#2
I_MDP_D2JI_MDP_D2
I_MDP_D3JI_MDP_D3
I_MDP_D#3 I_MDP_D#3J
I_MDP_D0 I_MDP_D0J
I_MDP_D#0 I_MDP_D#0J
I_MDP_D#1 I_MDP_D#1J
I_MDP_D1 I_MDP_D1J
I_MDP_MODE
PS8330B_CFG1
PS8330B_CFG0
IN_CAD_SRC
PS8330B_PEQ
I_MDP_HPD_R
IN0P_R
IN0N_R
IN1N_R
IN1P_R
IN2N_R
IN2P_R
IN3N_R
IN3P_R
I_MDP_D#0
I_MDP_D0
I_MDP_D#1
I_MDP_D1
I_MDP_D#2
I_MDP_D2
I_MDP_D#3
I_MDP_D3
I_MDP_AUX#_R
I_MDP_AUX#_R
I_MDP_AUX_R
I_MDP_AUX_R
I_MDP_HPD_R
PS8330B_CFG0
PS8330B_CFG1
PS8330B_PEQ
I_MDP_AUX_R I_MDP_AUX#_R
I_MDP_MODE
Schematic Diagrams
B - 28 mDP
B.Schematic Diagrams
mDP
Sheet 27 of 67
mDP

Clevo NH77DCQ Specifications

General

Brand	Clevo
Model	NH77DCQ
Category	Laptop
Language	English