5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
SSC CLOCK TERMINATION STUFF
ONLY WHEN SSC CLOCK NOT USED
Supports external Graphics
No integrated graphic and eDP
PU/PD for JTAG signals
S3 circuit:- DRAM PWR GOOD logic
Haswell Processor 2/7 ( MISC,JTAG,CLK )
BSS138 ( VGS 1.5V )
S3 circuit:- DRAM_RST# to memory
should be high during S3
DDR3 Compensation Signals
TRACE WIDTH 10MIL, LENGTH <500MILS
Processor Pullups/Pull downs
Buffered reset to CPU
CAD Note: Capacitor need to be placed
close to buffer output pin
DPLL_REF_CLKP
SSC_DPLL_REF_CLKP
SSC_DPLL_REF_CLKN
H_PROCHOT#
PCH_PLTRST_CPU
DPLL_REF_CLKN
XDP_DBR_R
XDP_TDO_R
XDP_TRST#
XDP_TCLK
H_CPUPWRGD_R
PMSYS_PWRGD_BUF
DPLL_REF_CLKP
CPUDRAMRST#
H_CATERR#
H_PROCHOT#
SM_RCOMP_0
SM_RCOMP_1
SM_RCOMP_2
BUF_CPU_RST#
PROC_DETECT#
PMSYS_PWRGD_BUF
SSC_DPLL_REF_CLKP
SSC_DPLL_REF_CLKN
H_CPUPWRGD_R
DPLL_REF_CLKN
SM_RCOMP_0
SM_RCOMP_1
SM_RCOMP_2
XDP_TCLK
XDP_TRST#
XDP_TMS
CPUDRAMRST#
XDP_TDO_R
XDP_TDI_R
XDP_PREQ#
XDP_BPM7
XDP_BPM6
XDP_BPM5
XDP_BPM4
XDP_BPM3
XDP_BPM2
XDP_BPM1
XDP_BPM0
XDP_DBR_R
XDP_PRDY#
H_PROCHOT#
XDP_TMS
XDP_TDI_R
XDP_PREQ#
XDP_TDO_R
CPU_RST#
BUF_CPU_RST#
VDDQ
3.3V
VDDQ
3.3V
1.05VS
3.3VS
VCCIO_OUT
VCCIO_OUT
1.05VS
1.05VS
1.05VS 6,38,39,55,57
VDDQ 6,9,10,11,12,52
DDR3_DRAMRST# 9,10,11,12
DRAMRST_CNTRL 33
3.3V 2,13,30,32,41,42,43,44,45,49,50,51,52,54,55,58,59,60
CLK_EXP_P40
CLK_EXP_N40
PLT_RST#35
3.3VS 9,10,11,12,13,14,15,16,17,32,33,34,35,37,38,39,40,41,43,44,45,46,48,49,50,51,54,57
PM_DRAM_PWRGD34
SUSB15,17,52,54,55
H_PECI37,48
H_PROCHOT#57
H_THRMTRIP#37
H_CPUPWRGD37
VCCIO_OUT 6,57
PCH_PLTRST_CPU37
H_PM_SYNC34
H_PROCHOT_EC48
CLK_DPNS_N40
CLK_DPNS_P40
CLK_DP_N40
CLK_DP_P40
Title
Size Document Number Rev
Date: S heet
of
6-71-P6500-D03
D03
[03] Processor 2/7-CLK,MISC
A3
377Monday, August 18, 2014
ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
P650SE
Title
Size Document Number Rev
Date: S heet
of
6-71-P6500-D03
D03
[03] Processor 2/7-CLK,MISC
A3
377Monday, August 18, 2014
ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
P650SE
Title
Size Document Number Rev
Date: S heet
of
6-71-P6500-D03
D03
[03] Processor 2/7-CLK,MISC
A3
377Monday, August 18, 2014
ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
P650SE
R329 51_04
R373 10K_04
R742 *100_1%_04
R371
*100K_04
R370
3.32K_1%_04
R348
100K_04
R746 0_04
R328 51_04
R201 0_04
Q25
*2SK3018S3
G
DS
R360 *0_04
U16
*MC74VHC1G08DFT1G
1
2
5
4
3
R372
1.82K_1%_04
R349 56_1%_04
R365
1K_04
R350 62_04
R203 *1K_04
R211 *1K_04
C503 *0.1u_16V_Y5V_04
R745 51_04
R359
4.99K_1%_04
R354
*100K_04
R200 0_04
C494
0.047u_10V_X7R_04
R741 *10mil_short
R355 0_04
R356 75_1%_04R194 0_04
R352 *10mil_short
MISC
CLOCK
JTAG DDR3
PWRTHERMAL
HASWELL_BGA_E
2 OF 12
U104B
PROC_DETECT
C51
PLTRSTIN
L54
SM_RCOMP0
BB51
SM_RCOMP1
BB53
SM_RCOMP2
BB52
SM_DRAMRST
BE51
DPLL_REF_CLKP
AE6
PM_SYNC
D52
SM_DRAMPWROK
AP48
THERMTRIP
D53
PWRGOOD
F50
DPLL_REF_CLKN
AC6
BPM#5
P53
BPM#3
N50
BPM#4
R49
BPM#2
P49
BPM#1
R50
BPM#0
R51
DBR
F53
TDO
M49
TRST
M53
TDI
N49
TMS
M51
TCK
N54
PREQ
N52
PRDY
N53
PROCHOT
E50
PECI
G51
CATERR
G50
BPM#7
P51
BPM#6
U51
BCLKP
AA6
BCLKN
AB6
SSC_DPLL_REF_CLKP
Y6
SSC_DPLL_REF_CLKN
V6
C500
*0.1u_16V_Y5V_04
Q21
2SK3018S3
G
DS
R195 0_04
R369
*39_04
R744 51_04
R364 1K_04
R202 *10K_04
R199 *10K_04
R7511K_04
R358 100_1%_04
C502
47P_50V_NPO_04
R366
*200_04
R357 100_1%_04
R752 *10mil_short
R351 *10mil_short
R326 *100_04
R330 *51_04
R754
*1K_1%_04
Q20
2SK3018S3
G
DS
R368 0_04
R747 *0_04
R327 51_04
R757 *2K_1%_04
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