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Clevo W550SU1 - Page 60

Clevo W550SU1
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Schematic Diagrams
B - 4 Processor 2/7- CLK, MISC
B.Schematic Diagrams
Processor 2/7- CLK, MISC
Sheet 3 of 45
Processor 2/7 -
CLK, MISC
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Haswell Processor 2/7 ( CLK,MISC,JTAG )
Buffered reset to CPU
S3 circuit:- DRAM_RST# to memory
should be high during S3
CAD Note: Capacitor need to be placed
close to buffer output pin
TRACE WIDTH 10MIL, LENGTH <500MILS
Processor Pullups/Pull downs
If PROCHOT# is not used,
then it must be terminated
with a 56-ȍ +-5% pull-up
resistor to 1.05VS_VTT .
DDR3 Compensation Signals
S3 circuit:- DRAM PWR GOOD lCIRCUIT
PU/PD for JTAG signals
SSC CLOCK TERMINATION
STUFF R4R15 & R4R12
ONLY WHEN SSC CLOCK
NOT USED
BUF_CPU_RST#
CPUDRAMRST#
SKTOCC#
H_CATERR#
H_PECI_ISO
H_PROCHOT#_D
H_THRMTRIP_R_N
H_CPUPWRGD H_CPUPWRGD_R
VDDPWRGOOD_RPMSYS_PWRGD_BUF XDP_DBR_R
XDP_TDO_R
XDP_TDI_R
XDP_TCLK
XDP_TRST#
XDP_TMS
SM_RCOMP_0
SM_RCOMP_1
SM_RCOMP_2
CPUDRAMRST#
XDP_PREQ#
XDP_PRDY#
H_CPUPWRGD_R
H_PROCHOT#
SM_RCOMP_0
SM_RCOMP_1
SM_RCOMP_2
XDP_DBR_R
XDP_TRST#
H_THRMTRIP_R_N
XDP_TCLK
XDP_TDO_R
PCH_SSC_P
PCH_SSC_N
PCH_SSC_N
PCH_SSC_P
BUF_CPU_RST# CPU_RST_N_R
XDP_BPM6
XDP_BPM5
XDP_BPM3
XDP_BPM4
XDP_BPM2
XDP_BPM1
XDP_BPM0
XDP_BPM7
H_PROCHOT#
PMSYS_PWRGD_BUF
CPU_RST_N
XDP_TMS
XDP_TDI_R
XDP_PREQ#
3.3VS
1.05V_LAN_M
1.05V_LAN_M
VCCIO_OUT
1.05V_LAN_M VCCST
VCCST
VCCIO_OUT
V_VDDQ_DIMM
V_VDDQ_DIMM
1.05V_LAN_M
1.05V_LAN_M20,21,32,35,5
3.3V12,19,2,21,23,24,26,27,31,32,34
PLT_RST#17
3.3VS10,11,12,13,14,15,16,17,18,20,21,22,23,24,25,26,27,28,29,30,31,35,6,9
DRAMRST_CNTRL 10,15,9
DDR3_DRAMRST# 10,9
H_PROCHOT_EC30
VCCIO_OUT5,6
H_PECI18,30
H_THRMTRIP_R_N18
H_PM_SYNC16
H_CPUPWRGD18
PCH_CK_DP_N22
PCH_CK_DP_P22
CLK_EXP_P22
CLK_EXP_N22
PCH_SSC_N22
PCH_SSC_P22
CPU_RST_N18
H_PROCHOT#35
V_VDDQ_DIMM10,34,5,9
PM_DRAM_PWRGD16
Title
Size
Document Number Re v
Date: Sheet
of
6-71-W54S0-D02A
2.0A
[03] Haswell 2/7-CLK/MISC
A3
345Wednesday, September 25, 2013
ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
6-7P-W5409-002
Title
Size
Document Number Re v
Date: Sheet
of
6-71-W54S0-D02A
2.0A
[03] Haswell 2/7-CLK/MISC
A3
345Wednesday, September 25, 2013
ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
6-7P-W5409-002
Title
Size
Document Number Re v
Date: Sheet
of
6-71-W54S0-D02A
2.0A
[03] Haswell 2/7-CLK/MISC
A3
345Wednesday, September 25, 2013
ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
6-7P-W5409-002
Q14
2SK3018S3
G
DS
R29710K_04
R301*100_04
R314 *0_04
R307 *1K_04
R302 *51_04
R70 0_04
R44 *51_04
R317
100K_04
Q15
2SK3018S3
G
DS
R45
*10K_04
R303 51_04
R326
1K_04
R322
4.99K_1%_04
R328 100_1%_04
R40 *51_04
R30962_04
R300
*51_04
R323 *0_04
C340
0.047u_10V_X7R_04
R76 *20mil_04
R312*75_04
R319
*1K_1%_04
R38 *51_04
R299
*100_04
R298 *20mil_04
R47
*10K_04
C50
*22u_6.3V_X5R_08
R313 *20mil_04
R324 75_1%_04
Haswell rPGA EDS
JTAG
CLOCK
THERMAL
MISC
DDR3
PWR
2 OF 9
U17B
THERMTRIP
AM35
SM_DRAMPWROK
AC10
PLTRSTIN
AT26
SKTOCC
AP32
CATERR
AN32
PECI
AR27
PROCHOT
AM30
DPLL_REF_CLKN
G28
DPLL_REF_CLKP
H28
SSC_DPLL_REF_CLKN
F27
SSC_DPLL_REF_CLKP
E27
BCLKN
D26
BCLKP
E26
SM_RCOMP_0
AP3
SM_RCOMP_1
AR3
SM_RCOMP_2
AP2
SM_DRAMRST
AN3
PRDY
AR29
PREQ
AT29
TCK
AM34
TMS
AN33
TRST
AM33
TDI
AM31
TDO
AL33
DBR
AP33
BPM_N_0
AR30
BPM_N_1
AN31
BPM_N_2
AN29
BPM_N_3
AP31
BPM_N_4
AP30
BPM_N_5
AN28
BPM_N_6
AP29
BPM_N_7
AP28
PWRGOOD
AL34
PM_SYNC
AT28
FC
AK31
R315 *20mil_04
R325 1K_04
R321 *2K_1%_04
R77
10K_04
C338
47p_50V_NPO_04
R37 *0_04
R310 56_1%_04
R327 100_1%_04

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